From: Peter Griffin <peter.griffin@linaro.org>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
andre.draszik@linaro.org, willmcvicker@google.com,
kernel-team@android.com, s.nawrocki@samsung.com,
cw00.choi@samsung.com, mturquette@baylibre.com,
sboyd@kernel.org, semen.protsenko@linaro.org,
linux-clk@vger.kernel.org, jaewon02.kim@samsung.com
Subject: Re: [PATCH v2 3/3] clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
Date: Thu, 28 Mar 2024 11:36:15 +0000 [thread overview]
Message-ID: <CADrjBPpjK15MDTcSdOhiC6FnJcofDGArEvrkhdz+CHoFzpFheA@mail.gmail.com> (raw)
In-Reply-To: <20240326172813.801470-4-tudor.ambarus@linaro.org>
Hi Tudor,
On Tue, 26 Mar 2024 at 17:28, Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
>
> When SPI transfer is being prepared, the spi-s3c64xx driver will call
> clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK
> is a gate (leaf) clock, so it must propagate the rate change up the
> clock tree, so that corresponding MUX/DIV clocks can actually change
> their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for
> all USI instances in GS101 PERIC0: USI{1-8, 14}. This change involves the
> following clocks:
>
> PERIC0 USI*:
>
> Clock Div range MUX Selection
> -------------------------------------------------------------------
> gout_peric0_peric0_top0_ipclk_* - -
> dout_peric0_usi*_usi /1..16 -
> mout_peric0_usi*_usi_user - {24.5 MHz, 400 MHz}
>
> With input clock of 400 MHz this scheme provides the following IPCLK
> rate range, for each USI block:
>
> PERIC0 USI*: 1.5 MHz ... 400 MHz
>
> Accounting for internal /4 divider in SPI blocks, and because the max
> SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates:
>
> PERIC0 USI_SPI*: 384 KHz ... 49.9 MHz
>
> Which shall be fine for the applications of the SPI bus.
>
> Note that with this we allow the reparenting of the MUX_USIx clocks to
> OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the
> reparenting of a MUX_USI clock corresponds to a single instance of the
> USI IP. The datasheet mentions OSCCLK just in the low-power mode
> context, but the downstream driver reparents too the MUX_USI clocks to
> OSCCLK. Follow the downstream driver and do the same.
>
> Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0")
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> ---
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
regards,
Peter
prev parent reply other threads:[~2024-03-28 11:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-26 17:28 [PATCH v2 0/3] clk: samsung: introduce nMUX to reparent MUX clocks Tudor Ambarus
2024-03-26 17:28 ` [PATCH v2 1/3] clk: samsung: introduce nMUX for MUX clks that can reparented Tudor Ambarus
2024-03-26 17:43 ` André Draszik
2024-03-27 8:09 ` Tudor Ambarus
2024-03-28 9:56 ` Krzysztof Kozlowski
2024-03-28 11:14 ` Tudor Ambarus
2024-03-26 17:28 ` [PATCH v2 2/3] clk: samsung: gs101: propagate PERIC1 USI SPI clock rate Tudor Ambarus
2024-03-28 11:25 ` André Draszik
2024-03-28 11:33 ` Peter Griffin
2024-03-26 17:28 ` [PATCH v2 3/3] clk: samsung: gs101: propagate PERIC0 " Tudor Ambarus
2024-03-28 11:25 ` André Draszik
2024-03-28 11:36 ` Peter Griffin [this message]
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