From: "André Draszik" <andre.draszik@linaro.org>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Sam Protsenko <semen.protsenko@linaro.org>
Cc: "Peter Griffin" <peter.griffin@linaro.org>,
"Tudor Ambarus" <tudor.ambarus@linaro.org>,
"Will McVicker" <willmcvicker@google.com>,
kernel-team@android.com, linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
"André Draszik" <andre.draszik@linaro.org>
Subject: [PATCH 5/5] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()
Date: Tue, 07 May 2024 15:14:48 +0100 [thread overview]
Message-ID: <20240507-samsung-usb-phy-fixes-v1-5-4ccba5afa7cc@linaro.org> (raw)
In-Reply-To: <20240507-samsung-usb-phy-fixes-v1-0-4ccba5afa7cc@linaro.org>
While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk
support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set
on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with
the frequency of the reference clock for the USB2.0 phy instead.
I stumbled across this while adding support for the Google Tensor
gs101, but this should apply to E850 just the same.
Do so.
Fixes: 691525074db9 ("phy: exynos5-usbdrd: Add Exynos850 support")
Signed-off-by: André Draszik <andre.draszik@linaro.org>
---
Feel free to drop the Fixes: if you think that is unwarranted here.
v2: add missing bitfield.h include (seems this is implied on some
platforms, but not on others)
---
drivers/phy/samsung/phy-exynos5-usbdrd.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 1da7a4881f72..15be966b50ae 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -8,6 +8,7 @@
* Author: Vivek Gautam <gautam.vivek@samsung.com>
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -141,6 +142,9 @@
#define CLKRST_PORT_RST BIT(1)
#define CLKRST_LINK_SW_RST BIT(0)
+#define EXYNOS850_DRD_SSPPLLCTL 0x30
+#define SSPPLLCTL_FSEL GENMASK(2, 0)
+
#define EXYNOS850_DRD_UTMI 0x50
#define UTMI_FORCE_VBUSVALID BIT(5)
#define UTMI_FORCE_BVALID BIT(4)
@@ -773,6 +777,31 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL;
writel(reg, regs_base + EXYNOS850_DRD_HSP);
+ reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL);
+ reg &= ~SSPPLLCTL_FSEL;
+ switch (phy_drd->extrefclk) {
+ case EXYNOS5_FSEL_50MHZ:
+ reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7);
+ break;
+ case EXYNOS5_FSEL_26MHZ:
+ reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6);
+ break;
+ case EXYNOS5_FSEL_24MHZ:
+ reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2);
+ break;
+ case EXYNOS5_FSEL_20MHZ:
+ reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1);
+ break;
+ case EXYNOS5_FSEL_19MHZ2:
+ reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0);
+ break;
+ default:
+ dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",
+ phy_drd->extrefclk);
+ break;
+ }
+ writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL);
+
/* Power up PHY analog blocks */
reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);
reg &= ~HSP_TEST_SIDDQ;
--
2.45.0.rc1.225.g2a3ae87e7f-goog
prev parent reply other threads:[~2024-05-07 14:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 14:14 [PATCH 0/5] a few fixes for the Samsung USB phy driver André Draszik
2024-05-07 14:14 ` [PATCH 1/5] phy: exynos5-usbdrd: uniform order of register bit macros André Draszik
2024-05-07 14:14 ` [PATCH 2/5] phy: exynos5-usbdrd: convert udelay() to fsleep() André Draszik
2024-05-07 14:14 ` [PATCH 3/5] phy: exynos5-usbdrd: make phy_isol() take a bool for clarity André Draszik
2024-05-07 14:14 ` [PATCH 4/5] phy: exynos5-usbdrd: fix definition of EXYNOS5_FSEL_26MHZ André Draszik
2024-05-07 14:14 ` André Draszik [this message]
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