From: Sam Protsenko <semen.protsenko@linaro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Sylwester Nawrocki <s.nawrocki@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>
Cc: Alim Akhtar <alim.akhtar@samsung.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tomasz Figa <tomasz.figa@gmail.com>,
linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 01/15] dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
Date: Sat, 24 Feb 2024 14:20:39 -0600 [thread overview]
Message-ID: <20240224202053.25313-2-semen.protsenko@linaro.org> (raw)
In-Reply-To: <20240224202053.25313-1-semen.protsenko@linaro.org>
Document CPU clock management unit compatibles and add corresponding
clock indices. Exynos850 has two CPU clusters (CL0 and CL1), each
containing 4 Cortex-A55 cores. CPU PLLs are generating main CPU clocks
for each cluster, and there are alternate ("switch") clocks that can be
used temporarily while re-configuring the PLL for the new rate. ACLK,
ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses.
CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to
change CPU rates. Also some CoreSight clocks can be derived from
DBG_USER (debug clock).
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v3:
- none
Changes in v2:
- none
.../clock/samsung,exynos850-clock.yaml | 42 +++++++++++++++
include/dt-bindings/clock/exynos850.h | 54 +++++++++++++++++++
2 files changed, 96 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index c752c8985a53..cdc5ded59fe5 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -36,6 +36,8 @@ properties:
- samsung,exynos850-cmu-aud
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
+ - samsung,exynos850-cmu-cpucl0
+ - samsung,exynos850-cmu-cpucl1
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-g3d
- samsung,exynos850-cmu-hsi
@@ -152,6 +154,46 @@ allOf:
- const: dout_core_mmc_embd
- const: dout_core_sss
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-cpucl0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CPUCL0 switch clock (from CMU_TOP)
+ - description: CPUCL0 debug clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cpucl0_switch
+ - const: dout_cpucl0_dbg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-cpucl1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CPUCL1 switch clock (from CMU_TOP)
+ - description: CPUCL1 debug clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cpucl1_switch
+ - const: dout_cpucl1_dbg
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index bc15108aa3c2..7666241520f8 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -88,6 +88,18 @@
#define CLK_MOUT_G3D_SWITCH 76
#define CLK_GOUT_G3D_SWITCH 77
#define CLK_DOUT_G3D_SWITCH 78
+#define CLK_MOUT_CPUCL0_DBG 79
+#define CLK_MOUT_CPUCL0_SWITCH 80
+#define CLK_GOUT_CPUCL0_DBG 81
+#define CLK_GOUT_CPUCL0_SWITCH 82
+#define CLK_DOUT_CPUCL0_DBG 83
+#define CLK_DOUT_CPUCL0_SWITCH 84
+#define CLK_MOUT_CPUCL1_DBG 85
+#define CLK_MOUT_CPUCL1_SWITCH 86
+#define CLK_GOUT_CPUCL1_DBG 87
+#define CLK_GOUT_CPUCL1_SWITCH 88
+#define CLK_DOUT_CPUCL1_DBG 89
+#define CLK_DOUT_CPUCL1_SWITCH 90
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
@@ -195,6 +207,48 @@
#define CLK_GOUT_CMGP_USI1_PCLK 14
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
+/* CMU_CPUCL0 */
+#define CLK_FOUT_CPUCL0_PLL 1
+#define CLK_MOUT_PLL_CPUCL0 2
+#define CLK_MOUT_CPUCL0_SWITCH_USER 3
+#define CLK_MOUT_CPUCL0_DBG_USER 4
+#define CLK_MOUT_CPUCL0_PLL 5
+#define CLK_DOUT_CPUCL0_CPU 6
+#define CLK_DOUT_CPUCL0_CMUREF 7
+#define CLK_DOUT_CPUCL0_PCLK 8
+#define CLK_DOUT_CLUSTER0_ACLK 9
+#define CLK_DOUT_CLUSTER0_ATCLK 10
+#define CLK_DOUT_CLUSTER0_PCLKDBG 11
+#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
+#define CLK_GOUT_CLUSTER0_ATCLK 13
+#define CLK_GOUT_CLUSTER0_PCLK 14
+#define CLK_GOUT_CLUSTER0_PERIPHCLK 15
+#define CLK_GOUT_CLUSTER0_SCLK 16
+#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17
+#define CLK_GOUT_CLUSTER0_CPU 18
+#define CLK_CLUSTER0_SCLK 19
+
+/* CMU_CPUCL1 */
+#define CLK_FOUT_CPUCL1_PLL 1
+#define CLK_MOUT_PLL_CPUCL1 2
+#define CLK_MOUT_CPUCL1_SWITCH_USER 3
+#define CLK_MOUT_CPUCL1_DBG_USER 4
+#define CLK_MOUT_CPUCL1_PLL 5
+#define CLK_DOUT_CPUCL1_CPU 6
+#define CLK_DOUT_CPUCL1_CMUREF 7
+#define CLK_DOUT_CPUCL1_PCLK 8
+#define CLK_DOUT_CLUSTER1_ACLK 9
+#define CLK_DOUT_CLUSTER1_ATCLK 10
+#define CLK_DOUT_CLUSTER1_PCLKDBG 11
+#define CLK_DOUT_CLUSTER1_PERIPHCLK 12
+#define CLK_GOUT_CLUSTER1_ATCLK 13
+#define CLK_GOUT_CLUSTER1_PCLK 14
+#define CLK_GOUT_CLUSTER1_PERIPHCLK 15
+#define CLK_GOUT_CLUSTER1_SCLK 16
+#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17
+#define CLK_GOUT_CLUSTER1_CPU 18
+#define CLK_CLUSTER1_SCLK 19
+
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
#define CLK_MOUT_G3D_PLL 2
--
2.39.2
next prev parent reply other threads:[~2024-02-24 20:20 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-24 20:20 [PATCH v3 00/15] clk: samsung: Add CPU clocks for Exynos850 Sam Protsenko
2024-02-24 20:20 ` Sam Protsenko [this message]
2024-02-25 16:10 ` (subset) [PATCH v3 01/15] dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1 Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 02/15] clk: samsung: Improve clk-cpu.c style Sam Protsenko
2024-02-25 16:10 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 03/15] clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c Sam Protsenko
2024-02-25 16:10 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 04/15] clk: samsung: Reduce params count in exynos_register_cpu_clock() Sam Protsenko
2024-02-25 16:10 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 05/15] clk: samsung: Use single CPU clock notifier callback for all chips Sam Protsenko
2024-02-25 16:10 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 06/15] clk: samsung: Group CPU clock functions by chip Sam Protsenko
2024-02-25 16:10 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 07/15] clk: samsung: Pass actual CPU clock registers base to CPU_CLK() Sam Protsenko
2024-02-25 16:11 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 08/15] clk: samsung: Pass register layout type explicitly to CLK_CPU() Sam Protsenko
2024-02-25 16:11 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 09/15] clk: samsung: Keep CPU clock chip specific data in a dedicated struct Sam Protsenko
2024-02-25 16:11 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 10/15] clk: samsung: Keep register offsets in chip specific structure Sam Protsenko
2024-02-25 16:01 ` Krzysztof Kozlowski
2024-02-25 16:11 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 11/15] clk: samsung: Pass mask to wait_until_mux_stable() Sam Protsenko
2024-02-25 16:11 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 12/15] clk: samsung: Add CPU clock support for Exynos850 Sam Protsenko
2024-02-25 16:11 ` (subset) " Krzysztof Kozlowski
2024-02-24 20:20 ` [PATCH v3 13/15] clk: samsung: Implement manual PLL control for ARM64 SoCs Sam Protsenko
2024-02-25 16:09 ` Krzysztof Kozlowski
2024-03-01 0:33 ` Sam Protsenko
2024-02-24 20:20 ` [PATCH v3 14/15] clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1 Sam Protsenko
2024-02-24 20:20 ` [PATCH v3 15/15] arm64: dts: exynos: Add CPU clocks for Exynos850 Sam Protsenko
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