From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Ian Rogers <irogers@google.com>,
Samuel Holland <samuel.holland@sifive.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Namhyung Kim <namhyung@kernel.org>
Subject: Re: [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Date: Sat, 11 May 2024 12:53:34 -0300 [thread overview]
Message-ID: <Zj-UfsmiG3GU4S88@x1> (raw)
In-Reply-To: <20240509021531.680920-1-samuel.holland@sifive.com>
On Wed, May 08, 2024 at 07:14:53PM -0700, Samuel Holland wrote:
> This series updates the PMU event JSON files to add support for newer
> SiFive CPUs, including those used in the upcoming HiFive Premier P550
> board. Since most changes are incremental, symbolic links are used when
> a set of events is unchanged from the previous CPU series.
Ian, are you ok with this? Someone with such systems can provide some
Tested-by?
- Arnaldo
>
> Eric Lin (5):
> perf vendor events riscv: Update SiFive Bullet events
> perf vendor events riscv: Add SiFive Bullet version 0x07 events
> perf vendor events riscv: Add SiFive Bullet version 0x0d events
> perf vendor events riscv: Add SiFive P550 events
> perf vendor events riscv: Add SiFive P650 events
>
> Samuel Holland (2):
> perf vendor events riscv: Rename U74 to Bullet
> perf vendor events riscv: Remove leading zeroes
>
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 6 +-
> .../cycle-and-instruction-count.json | 12 +++
> .../arch/riscv/sifive/bullet-07/firmware.json | 1 +
> .../riscv/sifive/bullet-07/instruction.json | 1 +
> .../arch/riscv/sifive/bullet-07/memory.json | 1 +
> .../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++
> .../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++
> .../cycle-and-instruction-count.json | 1 +
> .../arch/riscv/sifive/bullet-0d/firmware.json | 1 +
> .../riscv/sifive/bullet-0d/instruction.json | 1 +
> .../arch/riscv/sifive/bullet-0d/memory.json | 1 +
> .../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++
> .../riscv/sifive/bullet-0d/watchpoint.json | 1 +
> .../sifive/{u74 => bullet}/firmware.json | 0
> .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
> .../arch/riscv/sifive/bullet/memory.json | 32 +++++++
> .../arch/riscv/sifive/bullet/microarch.json | 57 ++++++++++++
> .../arch/riscv/sifive/p550/firmware.json | 1 +
> .../arch/riscv/sifive/p550/instruction.json | 1 +
> .../arch/riscv/sifive/p550/memory.json | 47 ++++++++++
> .../arch/riscv/sifive/p550/microarch.json | 1 +
> .../p650/cycle-and-instruction-count.json | 1 +
> .../arch/riscv/sifive/p650/firmware.json | 1 +
> .../arch/riscv/sifive/p650/instruction.json | 1 +
> .../arch/riscv/sifive/p650/memory.json | 57 ++++++++++++
> .../arch/riscv/sifive/p650/microarch.json | 62 +++++++++++++
> .../arch/riscv/sifive/p650/watchpoint.json | 1 +
> .../arch/riscv/sifive/u74/instructions.json | 92 -------------------
> .../arch/riscv/sifive/u74/memory.json | 32 -------
> .../arch/riscv/sifive/u74/microarch.json | 57 ------------
> 30 files changed, 555 insertions(+), 182 deletions(-)
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
> rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
>
> --
> 2.44.0
>
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prev parent reply other threads:[~2024-05-11 15:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-09 2:14 [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Samuel Holland
2024-05-09 2:14 ` [PATCH 1/7] perf vendor events riscv: Rename U74 to Bullet Samuel Holland
2024-05-09 2:14 ` [PATCH 2/7] perf vendor events riscv: Remove leading zeroes Samuel Holland
2024-05-09 2:14 ` [PATCH 3/7] perf vendor events riscv: Update SiFive Bullet events Samuel Holland
2024-05-09 2:14 ` [PATCH 4/7] perf vendor events riscv: Add SiFive Bullet version 0x07 events Samuel Holland
2024-05-09 2:14 ` [PATCH 5/7] perf vendor events riscv: Add SiFive Bullet version 0x0d events Samuel Holland
2024-05-09 2:14 ` [PATCH 6/7] perf vendor events riscv: Add SiFive P550 events Samuel Holland
2024-05-09 2:15 ` [PATCH 7/7] perf vendor events riscv: Add SiFive P650 events Samuel Holland
2024-05-11 15:53 ` Arnaldo Carvalho de Melo [this message]
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