From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
kvm@vger.kernel.org
Cc: will@kernel.org, julien.thierry.kdev@gmail.com,
apatel@ventanamicro.com, greentime.hu@sifive.com,
vincent.chen@sifive.com,
Yong-Xuan Wang <yongxuan.wang@sifive.com>
Subject: [kvmtool PATCH v2 1/1] riscv: Fix the hart bit setting of AIA
Date: Wed, 15 May 2024 17:19:02 +0800 [thread overview]
Message-ID: <20240515091902.28368-1-yongxuan.wang@sifive.com> (raw)
In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.
However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.
Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.
[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
Changelog
v2:
- update commit message
---
riscv/aia.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/riscv/aia.c b/riscv/aia.c
index fe9399a8ffc1..21d9704145d0 100644
--- a/riscv/aia.c
+++ b/riscv/aia.c
@@ -164,7 +164,7 @@ static int aia__init(struct kvm *kvm)
ret = ioctl(aia_fd, KVM_SET_DEVICE_ATTR, &aia_nr_sources_attr);
if (ret)
return ret;
- aia_hart_bits = fls_long(kvm->nrcpus);
+ aia_hart_bits = fls_long(kvm->nrcpus - 1);
ret = ioctl(aia_fd, KVM_SET_DEVICE_ATTR, &aia_hart_bits_attr);
if (ret)
return ret;
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next reply other threads:[~2024-05-15 9:19 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 9:19 Yong-Xuan Wang [this message]
2024-05-15 14:44 ` [kvmtool PATCH v2 1/1] riscv: Fix the hart bit setting of AIA Andrew Jones
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240515091902.28368-1-yongxuan.wang@sifive.com \
--to=yongxuan.wang@sifive.com \
--cc=apatel@ventanamicro.com \
--cc=greentime.hu@sifive.com \
--cc=julien.thierry.kdev@gmail.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=vincent.chen@sifive.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).