From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
devicetree@vger.kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
conor.dooley@microchip.com, anup@brainfault.org,
atishp@atishpatra.org, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
christoph.muellner@vrull.eu, heiko@sntech.de,
charlie@rivosinc.com, David.Laight@aculab.com,
parri.andrea@gmail.com, luxu.kernel@bytedance.com
Subject: Re: [PATCH v3 2/6] dt-bindings: riscv: Add Zawrs ISA extension description
Date: Fri, 26 Apr 2024 17:41:18 +0100 [thread overview]
Message-ID: <20240426-cogwheel-levers-948f454caa7e@spud> (raw)
In-Reply-To: <20240426100820.14762-10-ajones@ventanamicro.com>
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On Fri, Apr 26, 2024 at 12:08:22PM +0200, Andrew Jones wrote:
> Add description for the Zawrs (Wait-on-Reservation-Set) ISA extension
> which was ratified in commit 98918c844281 of riscv-isa-manual.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
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next prev parent reply other threads:[~2024-04-26 16:41 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 10:08 [PATCH v3 0/6] riscv: Apply Zawrs when available Andrew Jones
2024-04-26 10:08 ` [PATCH v3 1/6] riscv: Provide a definition for 'pause' Andrew Jones
2024-04-26 10:08 ` [PATCH v3 2/6] dt-bindings: riscv: Add Zawrs ISA extension description Andrew Jones
2024-04-26 16:41 ` Conor Dooley [this message]
2024-04-26 10:08 ` [PATCH v3 3/6] riscv: Add Zawrs support for spinlocks Andrew Jones
2024-04-26 10:08 ` [PATCH v3 4/6] riscv: hwprobe: export Zawrs ISA extension Andrew Jones
2024-04-26 10:08 ` [PATCH v3 5/6] KVM: riscv: Support guest wrs.nto Andrew Jones
2024-04-26 10:08 ` [PATCH v3 6/6] KVM: riscv: selftests: Add Zawrs extension to get-reg-list test Andrew Jones
2024-06-03 12:36 ` [PATCH v3 0/6] riscv: Apply Zawrs when available Andrew Jones
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