* [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates
@ 2022-09-27 11:19 Conor Dooley
2022-09-27 11:19 ` [PATCH v6 01/11] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
` (12 more replies)
0 siblings, 13 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
Resending with an extra patch making some more memory map changes that
are to be introduced in the v2022.10 reference design. Since the
v2022.10 and v2022.09 reference designs both indepedently break
backwards compat, v2022.09 is not compatible with <= v2022.05 and
v2022.10 is not compatible with v2022.09, I am doing the jump directly
to v2022.10 rather than putting an intermediate step at v2022.09.
I did not drop Krzysztof's Ack on patch 1 as s/09/10 has no impact on
the correctness of the binding.
--8<---
Hey all,
Some 6.1 targeted changes here.
Firstly, two new dev kits (one first-party & one from Aries Embedded).
They've been sitting in our vendor tree, so are being sent where they
belong.
Secondly, another release of our reference design for the Icicle kit
is due in September. Usually these do not really change much for the
devicetree, but this time around a pair of changes impact the memory
map.
The first of these is adding dma-ranges to the pcie controller. The
controller had some issues to begin with & with the current reference
design (v2022.05) would not work with mainline Linux nor has it since
reference design v2021.08. A combination of the property, a change
to the FPGA design & a small fix to the driver will get it working
with mainline again. The other non-backwards compatible change to the
reference design is moves of the peripherals instantiated in the
fabric. Currently they are fairly spread out & a common complaint has
been that this leaves little room in the fic3 section of the memory map
for custom peripherals without removing the existing ones.
This series depends on [0] so as not to add dtbs_check warnings. The
fabric clock support is added by [1].
Thanks,
Conor.
Changes since v5:
- swap v2022.09 for v2022.10 in the binding
- add a patch with the v2022.10 memory map changes
Changes since v4:
- fix the incompatible interrupts on m100pfsevp
Changes since v3:
- add an extra patch reducing the fic3 clock rate
Changes since v2:
- drop the sd & emmc versions of the aries devicetree
- remove a extra newline
Changes since v1:
- made the polarberry part of an enum in patch 1
0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/
1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/
Conor Dooley (9):
dt-bindings: riscv: microchip: document icicle reference design
dt-bindings: riscv: microchip: document the aries m100pfsevp
riscv: dts: microchip: add pci dma ranges for the icicle kit
riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
riscv: dts: microchip: icicle: update pci address properties
riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
riscv: dts: microchip: reduce the fic3 clock rate
riscv: dts: microchip: add a devicetree for aries' m100pfsevp
riscv: dts: microchip: update memory configuration for v2022.10
Shravan Chippa (1):
dt-bindings: riscv: microchip: document the sev kit
Vattipalli Praveen (1):
riscv: dts: microchip: add sevkit device tree
.../devicetree/bindings/riscv/microchip.yaml | 20 +-
arch/riscv/boot/dts/microchip/Makefile | 2 +
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 43 ++++-
.../boot/dts/microchip/mpfs-icicle-kit.dts | 18 +-
.../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++
.../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++
.../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 +++++
.../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
arch/riscv/boot/dts/microchip/mpfs.dtsi | 30 ---
10 files changed, 511 insertions(+), 45 deletions(-)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
--
2.37.3
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v6 01/11] dt-bindings: riscv: microchip: document icicle reference design
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp Conor Dooley
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel, Krzysztof Kozlowski
The icicle kit reference design's v2022.09 release made some changes
to the memory map - including adding the ability to read the fabric
clock controllers via the system controller bus & making the PCI
controller work with upstream Linux.
While the PCI was not working in the v2022.03 design, so nothing is
broken there in terms of backwards compatibility, the fabric clocks
used in the v2022.03 design were chosen by the individual run of the
synthesis tool. In the v2022.09 reference design, the clocks are fixed
to use the "north west" fabric Clock Conditioning Circuitry.
In the v2022.10 release, the memory map on the DDR side is also
changing, so to avoid making a breaking change here twice, jump over the
v2022.09 release and straight to the v2022.10 one.
Make use of a new compatible to denote that v2022.{09,10} reference
design releases are not backwards compatible.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../devicetree/bindings/riscv/microchip.yaml | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 1aa7336a9672..5c1ad2108049 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -17,12 +17,18 @@ properties:
$nodename:
const: '/'
compatible:
- items:
- - enum:
- - microchip,mpfs-icicle-kit
- - microchip,mpfs-icicle-reference-rtlv2203
- - sundance,polarberry
- - const: microchip,mpfs
+ oneOf:
+ - items:
+ - enum:
+ - microchip,mpfs-icicle-reference-rtlv2203
+ - microchip,mpfs-icicle-reference-rtlv2210
+ - const: microchip,mpfs-icicle-kit
+ - const: microchip,mpfs
+
+ - items:
+ - enum:
+ - sundance,polarberry
+ - const: microchip,mpfs
additionalProperties: true
--
2.37.3
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-09-27 11:19 ` [PATCH v6 01/11] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 03/11] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel, Rob Herring
Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform.
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 5c1ad2108049..681cedc5578f 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -27,6 +27,7 @@ properties:
- items:
- enum:
+ - aries,m100pfsevp
- sundance,polarberry
- const: microchip,mpfs
--
2.37.3
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 03/11] dt-bindings: riscv: microchip: document the sev kit
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-09-27 11:19 ` [PATCH v6 01/11] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-09-27 11:19 ` [PATCH v6 02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel, Krzysztof Kozlowski
From: Shravan Chippa <shravan.chippa@microchip.com>
Update devicetree bindings document with PolarFire SoC Video Kit, known
by its "sev-kit" product code.
Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06
Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 681cedc5578f..2b8c6a695e99 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -28,6 +28,7 @@ properties:
- items:
- enum:
- aries,m100pfsevp
+ - microchip,mpfs-sev-kit
- sundance,polarberry
- const: microchip,mpfs
--
2.37.3
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (2 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 03/11] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
The recently removed, accidentally included, "matr0" property was used
in place of a dma-ranges property. The PCI controller is non-functional
with mainline Linux in the v2022.02 or later reference designs and has
not worked without configuration of address-translation since v2021.08.
Add the address translation that will be used by the v2022.09 reference
design & update the compatible used by the dts. Since this change is not
backwards compatible, update the compatible to denote this, jumping over
v2022.09 directly to v2022.10.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 7 ++++++-
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 0d28858b83f2..eec5aba43436 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,7 +2,8 @@
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/ {
- compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+ "microchip,mpfs";
core_pwm0: pwm@41000000 {
compatible = "microchip,corepwm-rtl-v4";
@@ -37,3 +38,7 @@ fabric_clk1: fabric-clk1 {
clock-frequency = <125000000>;
};
};
+
+&pcie {
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 044982a11df5..42d350fe6c6b 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -11,7 +11,8 @@
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+ "microchip,mpfs";
aliases {
ethernet0 = &mac1;
--
2.37.3
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (3 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 06/11] riscv: dts: microchip: icicle: update pci address properties Conor Dooley
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
In today's edition of moving things around:
The PCIe root port on PolarFire SoC is more part of the FPGA than of
the Core Complex. It is located on the other side of the chip and,
apart from its interrupts, most of its configuration is determined
by the FPGA bitstream rather. This includes:
- address translation in both directions
- the addresses at which the config and data regions appear to the
core complex
- the clocks used by the AXI bus
- the plic interrupt used
Moving the PCIe node to the -fabric.dtsi makes it clearer than a
singular configuration for root port is not correct & allows the
base SoC dtsi to be more easily included.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 32 +++++++++++++++++--
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++++++++++++++++
arch/riscv/boot/dts/microchip/mpfs.dtsi | 30 -----------------
3 files changed, 58 insertions(+), 33 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index eec5aba43436..688ef0fc5a64 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -37,8 +37,34 @@ fabric_clk1: fabric-clk1 {
#clock-cells = <0>;
clock-frequency = <125000000>;
};
-};
-&pcie {
- dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ status = "disabled";
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
index 49380c428ec9..67303bc0e451 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -13,4 +13,33 @@ fabric_clk1: fabric-clk1 {
#clock-cells = <0>;
clock-frequency = <125000000>;
};
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ status = "disabled";
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
};
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 45e3cc659882..79fd8dfce96f 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -464,36 +464,6 @@ usb: usb@20201000 {
status = "disabled";
};
- pcie: pcie@2000000000 {
- compatible = "microchip,pcie-host-1.0";
- #address-cells = <0x3>;
- #interrupt-cells = <0x1>;
- #size-cells = <0x2>;
- device_type = "pci";
- reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
- reg-names = "cfg", "apb";
- bus-range = <0x0 0x7f>;
- interrupt-parent = <&plic>;
- interrupts = <119>;
- interrupt-map = <0 0 0 1 &pcie_intc 0>,
- <0 0 0 2 &pcie_intc 1>,
- <0 0 0 3 &pcie_intc 2>,
- <0 0 0 4 &pcie_intc 3>;
- interrupt-map-mask = <0 0 0 7>;
- clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
- clock-names = "fic0", "fic1", "fic3";
- ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
- msi-parent = <&pcie>;
- msi-controller;
- microchip,axi-m-atr0 = <0x10 0x0>;
- status = "disabled";
- pcie_intc: legacy-interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
- };
-
mbox: mailbox@37020000 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
--
2.37.3
_______________________________________________
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linux-riscv@lists.infradead.org
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 06/11] riscv: dts: microchip: icicle: update pci address properties
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (4 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Conor Dooley
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
For the v2022.09 reference design the PCI root port's data region has
been moved to FIC1 from FIC0. This is a shorter path, allowing for
higher clock rates and improved through-put. As a result, the address at
which the PCIe's data region appears to the core complex has changed.
The config region's address is unchanged.
As FIC0 is no longer used, its clock can be removed too.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 688ef0fc5a64..9ca2ac4ad8e2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -38,13 +38,13 @@ fabric_clk1: fabric-clk1 {
clock-frequency = <125000000>;
};
- pcie: pcie@2000000000 {
+ pcie: pcie@3000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
- reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
reg-names = "cfg", "apb";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
@@ -54,9 +54,9 @@ pcie: pcie@2000000000 {
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
- clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
- clock-names = "fic0", "fic1", "fic3";
- ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ clocks = <&fabric_clk1>, <&fabric_clk3>;
+ clock-names = "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
msi-parent = <&pcie>;
msi-controller;
--
2.37.3
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (5 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 06/11] riscv: dts: microchip: icicle: update pci address properties Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 08/11] riscv: dts: microchip: reduce the fic3 clock rate Conor Dooley
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
When users try to add onto the reference design, they find that the
current addresses that peripherals connected to Fabric InterConnect
(FIC) 3 use are restrictive. For the v2022.09 reference design, the
peripherals have been shifted down, leaving more contiguous address
space for their custom IP/peripherals.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 9ca2ac4ad8e2..35030ea330ee 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -5,18 +5,18 @@ / {
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
- core_pwm0: pwm@41000000 {
+ core_pwm0: pwm@40000000 {
compatible = "microchip,corepwm-rtl-v4";
- reg = <0x0 0x41000000 0x0 0xF0>;
+ reg = <0x0 0x40000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
#pwm-cells = <2>;
clocks = <&fabric_clk3>;
status = "disabled";
};
- i2c2: i2c@44000000 {
+ i2c2: i2c@40000200 {
compatible = "microchip,corei2c-rtl-v7";
- reg = <0x0 0x44000000 0x0 0x1000>;
+ reg = <0x0 0x40000200 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&fabric_clk3>;
--
2.37.3
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 08/11] riscv: dts: microchip: reduce the fic3 clock rate
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (6 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 09/11] riscv: dts: microchip: add sevkit device tree Conor Dooley
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
For the v2022.09 release of the reference design, the fic3 clock rate
been reduced from 62.5 MHz to 50 MHz as it allows timing to be closed
significantly more quickly by customers who chose to build the
reference design themselves.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 35030ea330ee..b6bfe177ccb2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -29,7 +29,7 @@ i2c2: i2c@40000200 {
fabric_clk3: fabric-clk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <62500000>;
+ clock-frequency = <50000000>;
};
fabric_clk1: fabric-clk1 {
--
2.37.3
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 09/11] riscv: dts: microchip: add sevkit device tree
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (7 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 08/11] riscv: dts: microchip: reduce the fic3 clock rate Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
From: Vattipalli Praveen <praveen.kumar@microchip.com>
Add a basic dts for the Microchip Smart Embedded Vision dev kit.
The SEV kit is an upcoming first party board, featuring an MPFS250T and:
- Dual Sony Camera Sensors (IMX334)
- IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi
- Bluetooth 5 Low Energy
- 4 GB DDR4 x64
- 2 GB LPDDR4 x32
- 1 GB SPI Flash
- 8 GB eMMC flash & SD card slot (multiplexed)
- HDMI2.0 Video Input/Output
- MIPI DSI Output
- MIPI CSI-2 Input
Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06
Signed-off-by: Vattipalli Praveen <praveen.kumar@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 ++++++
.../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++++++
3 files changed, 191 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 39aae7b04f1c..f18477b2e86d 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
new file mode 100644
index 000000000000..8545baf4d129
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+/ {
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ status = "disabled";
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
new file mode 100644
index 000000000000..013cb666c72d
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-sev-kit-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC SEV Kit";
+ compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
+
+ aliases {
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <MTIMER_FREQ>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fabricbuf0ddrc: buffer@80000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80000000 0x0 0x2000000>;
+ };
+
+ fabricbuf1ddrnc: buffer@c4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xc4000000 0x0 0x4000000>;
+ };
+
+ fabricbuf2ddrncwcb: buffer@d4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0xd4000000 0x0 0x4000000>;
+ };
+ };
+
+ ddrc_cache: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x0 0x0 0x76000000>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
+
+&mac1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+};
+
+&mbox {
+ status = "okay";
+};
+
+&mmc {
+ status = "okay";
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+};
+
+&mmuart1 {
+ status = "okay";
+};
+
+&mmuart2 {
+ status = "okay";
+};
+
+&mmuart3 {
+ status = "okay";
+};
+
+&mmuart4 {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "otg";
+};
--
2.37.3
_______________________________________________
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (8 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 09/11] riscv: dts: microchip: add sevkit device tree Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:19 ` [PATCH v6 11/11] riscv: dts: microchip: update memory configuration for v2022.10 Conor Dooley
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
Add device trees for both configs used by the Aries Embedded
M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM,
featuring:
- 2GB DDR4 SDRAM dedicated to the HMS
- 512MB DDR4 SDRAM dedicated to the FPGA
- 32 MB SPI NOR Flash
- 4 GByte eMMC
and a carrier board with:
- 2x Gigabit Ethernet
- USB
- 2x UART
- 2x CAN
- TFT connector
- HSMC extension connector
- 3x PMOD extension connectors
- microSD-card slot
Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes
Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod
Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf
Co-developed-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++
.../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++
3 files changed, 225 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index f18477b2e86d..7427a20934f3 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
new file mode 100644
index 000000000000..7b9ee13b6a3a
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+/ {
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ status = "disabled";
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
new file mode 100644
index 000000000000..184cb36a175e
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Original all-in-one devicetree:
+ * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
+ * Rewritten to use includes:
+ * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
+ */
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-m100pfs-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ 1000000
+
+/ {
+ model = "Aries Embedded M100PFEVPS";
+ compatible = "aries,m100pfsevp", "microchip,mpfs";
+
+ aliases {
+ ethernet0 = &mac0;
+ ethernet1 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
+ gpio0 = &gpio0;
+ gpio1 = &gpio2;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <MTIMER_FREQ>;
+ };
+
+ ddrc_cache_lo: memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+ ddrc_cache_hi: memory@1040000000 {
+ device_type = "memory";
+ reg = <0x10 0x40000000 0x0 0x40000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&gpio0 {
+ interrupts = <13>, <14>, <15>, <16>,
+ <17>, <18>, <19>, <20>,
+ <21>, <22>, <23>, <24>,
+ <25>, <26>;
+ ngpios = <14>;
+ status = "okay";
+
+ pmic-irq-hog {
+ gpio-hog;
+ gpios = <13 0>;
+ input;
+ };
+
+ /* Set to low for eMMC, high for SD-card */
+ mmc-sel-hog {
+ gpio-hog;
+ gpios = <12 0>;
+ output-high;
+ };
+};
+
+&gpio2 {
+ interrupts = <13>, <14>, <15>, <16>,
+ <17>, <18>, <19>, <20>,
+ <21>, <22>, <23>, <24>,
+ <25>, <26>, <27>, <28>,
+ <29>, <30>, <31>, <32>,
+ <33>, <34>, <35>, <36>,
+ <37>, <38>, <39>, <40>,
+ <41>, <42>, <43>, <44>;
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&mac1 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&mbox {
+ status = "okay";
+};
+
+&mmc {
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ no-1-8-v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ disable-wp;
+ status = "okay";
+};
+
+&mmuart1 {
+ status = "okay";
+};
+
+&mmuart2 {
+ status = "okay";
+};
+
+&mmuart3 {
+ status = "okay";
+};
+
+&mmuart4 {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
--
2.37.3
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 11/11] riscv: dts: microchip: update memory configuration for v2022.10
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (9 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley
@ 2022-09-27 11:19 ` Conor Dooley
2022-09-27 11:22 ` [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-09-27 18:33 ` Conor Dooley
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daire McNamara,
Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
In the v2022.10 reference design, the seg registers are going to be
changed, resulting in a required change to the memory map in Linux.
A small 4M reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload.bin between
reboots of a specific context.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 42d350fe6c6b..31f88cb4d5e5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -33,15 +33,26 @@ cpus {
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x2e000000>;
+ reg = <0x0 0x80000000 0x0 0x40000000>;
status = "okay";
};
ddrc_cache_hi: memory@1000000000 {
device_type = "memory";
- reg = <0x10 0x0 0x0 0x40000000>;
+ reg = <0x10 0x40000000 0x0 0x40000000>;
status = "okay";
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss_payload: region@BFC00000 {
+ reg = <0x0 0xBFC00000 0x0 0x400000>;
+ no-map;
+ };
+ };
};
&core_pwm0 {
--
2.37.3
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (10 preceding siblings ...)
2022-09-27 11:19 ` [PATCH v6 11/11] riscv: dts: microchip: update memory configuration for v2022.10 Conor Dooley
@ 2022-09-27 11:22 ` Conor Dooley
2022-09-27 18:33 ` Conor Dooley
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 11:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Daire McNamara, Shravan Chippa
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Cyril Jean, Lewis Hanly,
Vattipalli Praveen, Wolfgang Grandegger, Hugh Breslin, devicetree,
linux-riscv, linux-kernel
On Tue, Sep 27, 2022 at 12:19:12PM +0100, Conor Dooley wrote:
> Resending with an extra patch making some more memory map changes that
> are to be introduced in the v2022.10 reference design. Since the
> v2022.10 and v2022.09 reference designs both indepedently break
> backwards compat, v2022.09 is not compatible with <= v2022.05 and
> v2022.10 is not compatible with v2022.09, I am doing the jump directly
> to v2022.10 rather than putting an intermediate step at v2022.09.
>
> I did not drop Krzysztof's Ack on patch 1 as s/09/10 has no impact on
> the correctness of the binding.
I had already applied v5, but I am going to apply this version instead.
I will send a PR once the v2022.10 reference design has been released on
the PolarFire SoC GitHub.
Thanks,
Conor.
>
> --8<---
> Hey all,
>
> Some 6.1 targeted changes here.
> Firstly, two new dev kits (one first-party & one from Aries Embedded).
> They've been sitting in our vendor tree, so are being sent where they
> belong.
>
> Secondly, another release of our reference design for the Icicle kit
> is due in September. Usually these do not really change much for the
> devicetree, but this time around a pair of changes impact the memory
> map.
>
> The first of these is adding dma-ranges to the pcie controller. The
> controller had some issues to begin with & with the current reference
> design (v2022.05) would not work with mainline Linux nor has it since
> reference design v2021.08. A combination of the property, a change
> to the FPGA design & a small fix to the driver will get it working
> with mainline again. The other non-backwards compatible change to the
> reference design is moves of the peripherals instantiated in the
> fabric. Currently they are fairly spread out & a common complaint has
> been that this leaves little room in the fic3 section of the memory map
> for custom peripherals without removing the existing ones.
>
> This series depends on [0] so as not to add dtbs_check warnings. The
> fabric clock support is added by [1].
>
> Thanks,
> Conor.
>
> Changes since v5:
> - swap v2022.09 for v2022.10 in the binding
> - add a patch with the v2022.10 memory map changes
>
> Changes since v4:
> - fix the incompatible interrupts on m100pfsevp
>
> Changes since v3:
> - add an extra patch reducing the fic3 clock rate
>
> Changes since v2:
> - drop the sd & emmc versions of the aries devicetree
> - remove a extra newline
>
> Changes since v1:
> - made the polarberry part of an enum in patch 1
>
> 0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/
> 1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/
>
> Conor Dooley (9):
> dt-bindings: riscv: microchip: document icicle reference design
> dt-bindings: riscv: microchip: document the aries m100pfsevp
> riscv: dts: microchip: add pci dma ranges for the icicle kit
> riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
> riscv: dts: microchip: icicle: update pci address properties
> riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
> riscv: dts: microchip: reduce the fic3 clock rate
> riscv: dts: microchip: add a devicetree for aries' m100pfsevp
> riscv: dts: microchip: update memory configuration for v2022.10
>
> Shravan Chippa (1):
> dt-bindings: riscv: microchip: document the sev kit
>
> Vattipalli Praveen (1):
> riscv: dts: microchip: add sevkit device tree
>
> .../devicetree/bindings/riscv/microchip.yaml | 20 +-
> arch/riscv/boot/dts/microchip/Makefile | 2 +
> .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 43 ++++-
> .../boot/dts/microchip/mpfs-icicle-kit.dts | 18 +-
> .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++
> .../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++
> .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++
> .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 +++++
> .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
> arch/riscv/boot/dts/microchip/mpfs.dtsi | 30 ---
> 10 files changed, 511 insertions(+), 45 deletions(-)
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
> create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
>
> --
> 2.37.3
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates
2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
` (11 preceding siblings ...)
2022-09-27 11:22 ` [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
@ 2022-09-27 18:33 ` Conor Dooley
12 siblings, 0 replies; 14+ messages in thread
From: Conor Dooley @ 2022-09-27 18:33 UTC (permalink / raw)
To: Daire McNamara, Shravan Chippa, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Palmer Dabbelt, Hugh Breslin, devicetree, Cyril Jean,
Paul Walmsley, Vattipalli Praveen, linux-riscv, linux-kernel,
Albert Ou, Wolfgang Grandegger, Lewis Hanly
From: Conor Dooley <conor.dooley@microchip.com>
On Tue, 27 Sep 2022 12:19:12 +0100, Conor Dooley wrote:
> Resending with an extra patch making some more memory map changes that
> are to be introduced in the v2022.10 reference design. Since the
> v2022.10 and v2022.09 reference designs both indepedently break
> backwards compat, v2022.09 is not compatible with <= v2022.05 and
> v2022.10 is not compatible with v2022.09, I am doing the jump directly
> to v2022.10 rather than putting an intermediate step at v2022.09.
>
> [...]
Applied to dt-for-next (in place of v5). As I pointed out earlier, I
will not make a PR for this until the reference design is available
on the PolarFire SoC GitHub.
[01/11] dt-bindings: riscv: microchip: document icicle reference design
https://git.kernel.org/conor/c/a0d49a8f77f2
[02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp
https://git.kernel.org/conor/c/0ebdc51787db
[03/11] dt-bindings: riscv: microchip: document the sev kit
https://git.kernel.org/conor/c/db3d481698ef
[04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit
https://git.kernel.org/conor/c/f890e67f292d
[05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
https://git.kernel.org/conor/c/99d451a7db16
[06/11] riscv: dts: microchip: icicle: update pci address properties
https://git.kernel.org/conor/c/6fc655ed4986
[07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
https://git.kernel.org/conor/c/ab291621a8b8
[08/11] riscv: dts: microchip: reduce the fic3 clock rate
https://git.kernel.org/conor/c/fa52935abef4
[09/11] riscv: dts: microchip: add sevkit device tree
https://git.kernel.org/conor/c/978a17d1a688
[10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp
https://git.kernel.org/conor/c/d49166646e44
[11/11] riscv: dts: microchip: update memory configuration for v2022.10
https://git.kernel.org/conor/c/6c1193301791
Thanks,
Conor.
_______________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-09-27 18:34 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
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2022-09-27 11:19 [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-09-27 11:19 ` [PATCH v6 01/11] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-09-27 11:19 ` [PATCH v6 02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp Conor Dooley
2022-09-27 11:19 ` [PATCH v6 03/11] dt-bindings: riscv: microchip: document the sev kit Conor Dooley
2022-09-27 11:19 ` [PATCH v6 04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit Conor Dooley
2022-09-27 11:19 ` [PATCH v6 05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Conor Dooley
2022-09-27 11:19 ` [PATCH v6 06/11] riscv: dts: microchip: icicle: update pci address properties Conor Dooley
2022-09-27 11:19 ` [PATCH v6 07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Conor Dooley
2022-09-27 11:19 ` [PATCH v6 08/11] riscv: dts: microchip: reduce the fic3 clock rate Conor Dooley
2022-09-27 11:19 ` [PATCH v6 09/11] riscv: dts: microchip: add sevkit device tree Conor Dooley
2022-09-27 11:19 ` [PATCH v6 10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Conor Dooley
2022-09-27 11:19 ` [PATCH v6 11/11] riscv: dts: microchip: update memory configuration for v2022.10 Conor Dooley
2022-09-27 11:22 ` [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Conor Dooley
2022-09-27 18:33 ` Conor Dooley
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