From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Maciej W . Rozycki" <macro@orcam.me.uk>,
"Jonathan Cameron" <Jonathan.Cameron@Huawei.com>,
"Lukas Wunner" <lukas@wunner.de>,
"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
linux-pm@vger.kernel.org, "Jonathan Corbet" <corbet@lwn.net>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: "Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Amit Kucheria" <amitk@kernel.org>,
"Zhang Rui" <rui.zhang@intel.com>,
"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH v6 1/8] PCI: Protect Link Control 2 Register with RMW locking
Date: Thu, 16 May 2024 12:32:15 +0300 [thread overview]
Message-ID: <20240516093222.1684-2-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20240516093222.1684-1-ilpo.jarvinen@linux.intel.com>
PCIe Bandwidth Controller performs RMW accesses the Link Control 2
Register which can occur concurrently to other sources of Link Control
2 Register writes. Therefore, add Link Control 2 Register among the PCI
Express Capability Registers that need RMW locking.
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Lukas Wunner <lukas@wunner.de>
---
Documentation/PCI/pciebus-howto.rst | 14 +++++++++-----
include/linux/pci.h | 1 +
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst
index a0027e8fb0d0..cd7857dd37aa 100644
--- a/Documentation/PCI/pciebus-howto.rst
+++ b/Documentation/PCI/pciebus-howto.rst
@@ -217,8 +217,12 @@ capability structure except the PCI Express capability structure,
that is shared between many drivers including the service drivers.
RMW Capability accessors (pcie_capability_clear_and_set_word(),
pcie_capability_set_word(), and pcie_capability_clear_word()) protect
-a selected set of PCI Express Capability Registers (Link Control
-Register and Root Control Register). Any change to those registers
-should be performed using RMW accessors to avoid problems due to
-concurrent updates. For the up-to-date list of protected registers,
-see pcie_capability_clear_and_set_word().
+a selected set of PCI Express Capability Registers:
+
+* Link Control Register
+* Root Control Register
+* Link Control 2 Register
+
+Any change to those registers should be performed using RMW accessors to
+avoid problems due to concurrent updates. For the up-to-date list of
+protected registers, see pcie_capability_clear_and_set_word().
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 16493426a04f..93faaf08965e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1273,6 +1273,7 @@ static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
{
switch (pos) {
case PCI_EXP_LNKCTL:
+ case PCI_EXP_LNKCTL2:
case PCI_EXP_RTCTL:
return pcie_capability_clear_and_set_word_locked(dev, pos,
clear, set);
--
2.39.2
next prev parent reply other threads:[~2024-05-16 9:33 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-16 9:32 [PATCH v6 0/8] PCI: Add PCIe bandwidth controller Ilpo Järvinen
2024-05-16 9:32 ` Ilpo Järvinen [this message]
2024-05-16 9:32 ` [PATCH v6 2/8] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 3/8] PCI: Refactor pcie_update_link_speed() Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 4/8] PCI/quirks: Abstract LBMS seen check into own function Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 5/8] PCI/bwctrl: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 6/8] PCI/bwctrl: Add API to set PCIe Link Speed Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 7/8] thermal: Add PCIe cooling driver Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 8/8] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
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