Re: [PATCH 1/3] dt-bindings: phy: airoha: Add binding doc for PCIe PHY driver

From: Lorenzo Bianconi <lorenzo@kernel.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: linux-phy@lists.infradead.org, vkoul@kernel.org,
	kishon@kernel.org, lorenzo.bianconi83@gmail.com,
	conor@kernel.org, linux-arm-kernel@lists.infradead.org,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org, nbd@nbd.name,
	john@phrozen.org, dd@embedd.com, catalin.marinas@arm.com,
	will@kernel.org, upstream@airoha.com
Subject: Re: [PATCH 1/3] dt-bindings: phy: airoha: Add binding doc for PCIe PHY driver
Date: Mon, 13 May 2024 18:54:51 +0200	[thread overview]
Message-ID: <ZkJF2w0f2L6nOtKP@lore-desk> (raw)
In-Reply-To: <b65a6290-1500-42bc-815c-d88dd52dd8ac@collabora.com>

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> Il 12/05/24 17:27, Lorenzo Bianconi ha scritto:
> > Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY
> > driver.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >   .../bindings/phy/airoha,pcie-phy.yaml         | 55 +++++++++++++++++++
> >   1 file changed, 55 insertions(+)
> >   create mode 100644 Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
> > new file mode 100644
> > index 000000000000..443d7e717296
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml
> 
> airoha,en7581-pcie-phy.yaml

ack, I will fix it.

> 
> > @@ -0,0 +1,55 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/airoha,pcie-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Airoha PCIe PHY
> 
> title: Airoha EN7581 PCI-Express PHY

ack, I will fix it.

> 
> > +
> > +maintainers:
> > +  - Lorenzo Bianconi <lorenzo@kernel.org>
> > +
> > +description: |
> > +  The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
> > +
> > +properties:
> > +  compatible:
> > +    const: airoha,en7581-pcie-phy
> > +
> > +  reg:
> > +    maxItems: 3
> > +
> > +  reg-names:
> > +    items:
> > +      - const: csr_2l
> > +      - const: pma0
> > +      - const: pma1
> > +
> > +  "#phy-cells":
> > +    const: 0
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - "#phy-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/phy/phy.h>
> > +
> > +    bus {
> 
> Shouldn't this realistically be 'soc' instead?

ack, I will fix it.

Regards,
Lorenzo

> 
> Cheers,
> Angelo
> 
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        phy@11e80000 {
> > +            compatible = "airoha,en7581-pcie-phy";
> > +            #phy-cells = <0>;
> > +            reg = <0x0 0x1fa5a000 0x0 0xfff>,
> > +                  <0x0 0x1fa5b000 0x0 0xfff>,
> > +                  <0x0 0x1fa5c000 0x0 0xfff>;
> > +            reg-names = "csr_2l", "pma0", "pma1";
> > +        };
> > +    };
> 
> 
> 

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