From: Philipp Zabel <p.zabel@pengutronix.de>
To: forbidden405@outlook.com, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Jiancheng Xue <xuejiancheng@hisilicon.com>,
Shawn Guo <shawn.guo@linaro.org>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Kishon Vijay Abraham I <kishon@ti.com>,
David Yang <mmyangfl@gmail.com>
Subject: Re: [PATCH RFC v3 4/5] phy: hisilicon: hisi-inno-phy: add support for Hi3798MV200 INNO PHY
Date: Wed, 21 Feb 2024 13:53:16 +0100 [thread overview]
Message-ID: <4bf4146749abb1500f8a412deb4d61ab0f3c80e6.camel@pengutronix.de> (raw)
In-Reply-To: <20240220-inno-phy-v3-4-893cdf8633b4@outlook.com>
On Di, 2024-02-20 at 05:28 +0800, Yang Xiwen via B4 Relay wrote:
> From: Yang Xiwen <forbidden405@outlook.com>
>
> Direct MMIO resgiter access is used by Hi3798MV200. For other models,
register
> of_iomap() returns 0 due to insufficient length. So they are unaffected.
>
> Also Hi3798MV200 INNO PHY has an extra reset required to be deasserted,
> switch to reset_control_bulk_() APIs to resolve this.
reset_control_array_()
apparently.
> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
> ---
> drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 65 ++++++++++++++++++------------
> 1 file changed, 39 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> index b7e740eb4752..5175e5a351ac 100644
> --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> @@ -10,6 +10,7 @@
> #include <linux/io.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/reset.h>
> @@ -43,6 +44,7 @@
> #define PHY_CLK_ENABLE BIT(2)
>
> struct hisi_inno_phy_port {
> + void __iomem *base;
> struct reset_control *utmi_rst;
> struct hisi_inno_phy_priv *priv;
> };
> @@ -50,7 +52,7 @@ struct hisi_inno_phy_port {
> struct hisi_inno_phy_priv {
> void __iomem *mmio;
> struct clk *ref_clk;
> - struct reset_control *por_rst;
> + struct reset_control *rsts;
> unsigned int type;
> struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
> };
> @@ -62,26 +64,31 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
> u32 val;
> u32 value;
>
> - if (priv->type == PHY_TYPE_0)
> - val = (data & PHY_TEST_DATA) |
> - ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) |
> - ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) |
> - PHY0_TEST_WREN | PHY0_TEST_RST;
> - else
> - val = (data & PHY_TEST_DATA) |
> - ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) |
> - ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) |
> - PHY1_TEST_WREN | PHY1_TEST_RST;
> - writel(val, reg);
> -
> - value = val;
> - if (priv->type == PHY_TYPE_0)
> - value |= PHY0_TEST_CLK;
> - else
> - value |= PHY1_TEST_CLK;
> - writel(value, reg);
> -
> - writel(val, reg);
> + if (priv->ports[port].base)
> + // stride is 4
> + writel(data, (u32 *)priv->ports[port].base + addr);
> + else {
> + if (priv->type == PHY_TYPE_0)
> + val = (data & PHY_TEST_DATA) |
> + ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) |
> + ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) |
> + PHY0_TEST_WREN | PHY0_TEST_RST;
> + else
> + val = (data & PHY_TEST_DATA) |
> + ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) |
> + ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) |
> + PHY1_TEST_WREN | PHY1_TEST_RST;
> + writel(val, reg);
> +
> + value = val;
> + if (priv->type == PHY_TYPE_0)
> + value |= PHY0_TEST_CLK;
> + else
> + value |= PHY1_TEST_CLK;
> + writel(value, reg);
> +
> + writel(val, reg);
> + }
> }
>
> static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
> @@ -104,7 +111,7 @@ static int hisi_inno_phy_init(struct phy *phy)
> return ret;
> udelay(REF_CLK_STABLE_TIME);
>
> - reset_control_deassert(priv->por_rst);
> + reset_control_deassert(priv->rsts);
> udelay(POR_RST_COMPLETE_TIME);
>
> /* Set up phy registers */
> @@ -122,7 +129,7 @@ static int hisi_inno_phy_exit(struct phy *phy)
> struct hisi_inno_phy_priv *priv = port->priv;
>
> reset_control_assert(port->utmi_rst);
> - reset_control_assert(priv->por_rst);
> + reset_control_assert(priv->rsts);
> clk_disable_unprepare(priv->ref_clk);
>
> return 0;
> @@ -158,15 +165,16 @@ static int hisi_inno_phy_probe(struct platform_device *pdev)
> if (IS_ERR(priv->ref_clk))
> return PTR_ERR(priv->ref_clk);
>
> - priv->por_rst = devm_reset_control_get_exclusive(dev, NULL);
> - if (IS_ERR(priv->por_rst))
> - return PTR_ERR(priv->por_rst);
> + priv->rsts = devm_reset_control_array_get(dev, false, false);
Please use devm_reset_control_array_get_exclusive() instead.
regards
Philipp
--
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linux-phy@lists.infradead.org
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next prev parent reply other threads:[~2024-02-21 12:53 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-19 21:27 [PATCH RFC v3 0/5] phy: hisi-inno-phy: add support for hi3798mv200-usb2-phy Yang Xiwen via B4 Relay
2024-02-19 21:27 ` [PATCH RFC v3 1/5] dt-bindings: phy: hisi-inno-usb2: convert to YAML Yang Xiwen via B4 Relay
2024-02-19 21:30 ` Krzysztof Kozlowski
2024-02-19 21:33 ` Yang Xiwen
2024-02-19 21:36 ` Krzysztof Kozlowski
2024-02-19 21:50 ` Yang Xiwen
2024-02-19 21:32 ` Krzysztof Kozlowski
2024-02-19 21:35 ` Yang Xiwen
2024-02-19 21:37 ` Krzysztof Kozlowski
2024-02-19 21:49 ` Yang Xiwen
2024-02-20 8:16 ` Krzysztof Kozlowski
2024-02-20 10:40 ` Yang Xiwen
2024-02-20 11:41 ` Krzysztof Kozlowski
2024-02-20 11:43 ` Krzysztof Kozlowski
2024-02-20 12:12 ` Yang Xiwen
2024-02-21 8:22 ` Krzysztof Kozlowski
2024-02-21 8:25 ` Krzysztof Kozlowski
2024-02-21 11:15 ` Yang Xiwen
2024-02-21 10:05 ` Yang Xiwen
2024-02-21 8:23 ` Krzysztof Kozlowski
2024-02-19 22:33 ` Rob Herring
2024-02-19 21:27 ` [PATCH RFC v3 2/5] arm64: dts: hi3798cv200: add hisilicon,inno-usb2-phy to compatible list Yang Xiwen via B4 Relay
2024-02-19 21:28 ` [PATCH RFC v3 3/5] phy: hisilicon: hisi-inno-phy: enable clocks for every ports Yang Xiwen via B4 Relay
2024-02-19 21:28 ` [PATCH RFC v3 4/5] phy: hisilicon: hisi-inno-phy: add support for Hi3798MV200 INNO PHY Yang Xiwen via B4 Relay
2024-02-19 21:34 ` Krzysztof Kozlowski
2024-02-19 21:37 ` Yang Xiwen
2024-02-21 12:53 ` Philipp Zabel [this message]
2024-02-19 21:28 ` [PATCH RFC v3 5/5] dt-bindings: phy: hisi-inno-usb2: add compatible of hisilicon,hi3798mv200-usb2-phy Yang Xiwen via B4 Relay
2024-02-19 21:35 ` Krzysztof Kozlowski
2024-02-20 8:18 ` Krzysztof Kozlowski
2024-02-20 9:25 ` Yang Xiwen
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