From: Conor Dooley <conor.dooley@microchip.com>
To: Roger Quadros <rogerq@kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
Swapnil Jakhade <sjakhade@cadence.com>, <vkoul@kernel.org>,
<kishon@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <mparab@cadence.com>,
<s-vadapalli@ti.com>
Subject: Re: [PATCH 1/5] dt-bindings: phy: cadence-torrent: Add second optional input reference clock
Date: Mon, 11 Dec 2023 12:59:09 +0000 [thread overview]
Message-ID: <20231211-saucy-carnation-bce003ea09dd@wendy> (raw)
In-Reply-To: <13c7fa70-ec60-44a7-aba7-5c4b0e21a755@kernel.org>
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On Mon, Dec 11, 2023 at 02:45:48PM +0200, Roger Quadros wrote:
> Hi Conor,
>
> On 24/07/2023 20:53, Conor Dooley wrote:
> > On Mon, Jul 24, 2023 at 04:59:58PM +0200, Swapnil Jakhade wrote:
> >> Torrent(SD0801) PHY supports two input reference clocks. Update bindings
> >> to support dual reference clock multilink configurations.
> >>
> >> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> >> ---
> >> .../bindings/phy/phy-cadence-torrent.yaml | 23 +++++++++++++------
> >> 1 file changed, 16 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> >> index dfb31314face..ddb86ee0cebf 100644
> >> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> >> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> >> @@ -33,16 +33,25 @@ properties:
> >>
> >> clocks:
> >> minItems: 1
> >> - maxItems: 2
> >> + maxItems: 3
> >> description:
> >> - PHY reference clock for 1 item. Must contain an entry in clock-names.
> >> - Optional Parent to enable output reference clock.
> >> + PHY input reference clocks (refclk & refclk1).
> >
> > "refclk" and "refclk1" don't seem like great names. What is each one
> > used for & should refclk1 be renamed to match its use case?
>
> All PHYs need one refclk input. "refclk"
> Some PHY variants can take a second refclk input. Both are refclks so it was
> chosen to add an "1" to the name to the 2nd refclk.
> Please suggest if you have a better idea. Thanks!
The existing second clock name (phy_en_refclk) might serve as
inspiration. What is the additional role that the second reference
serves?
>
> >
> >> + Optional Parent to enable output reference clock (phy_en_refclk).
> >>
> >> clock-names:
> >> - minItems: 1
> >> - items:
> >> - - const: refclk
> >> - - const: phy_en_refclk
> >> + oneOf:
> >> + - items:
> >> + - const: refclk
> >> + - items:
> >> + - const: refclk
> >> + - const: phy_en_refclk
> >> + - items:
> >> + - const: refclk
> >> + - const: refclk1
> >> + - items:
> >> + - const: refclk
> >> + - const: refclk1
> >> + - const: phy_en_refclk
> >>
> >> reg:
> >> minItems: 1
> >> --
> >> 2.34.1
> >>
>
> --
> cheers,
> -roger
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next prev parent reply other threads:[~2023-12-11 13:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-24 14:59 [PATCH 0/5] PHY: Add support for dual refclk configurations in Cadence Torrent PHY driver Swapnil Jakhade
2023-07-24 14:59 ` [PATCH 1/5] dt-bindings: phy: cadence-torrent: Add second optional input reference clock Swapnil Jakhade
2023-07-24 17:53 ` Conor Dooley
2023-12-11 12:45 ` Roger Quadros
2023-12-11 12:59 ` Conor Dooley [this message]
2023-07-26 17:05 ` Rob Herring
2023-07-24 14:59 ` [PATCH 2/5] phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration Swapnil Jakhade
2023-07-24 15:00 ` [PATCH 3/5] phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) " Swapnil Jakhade
2023-07-24 15:00 ` [PATCH 4/5] dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200 Swapnil Jakhade
2023-07-24 17:56 ` Conor Dooley
2023-12-11 12:47 ` Roger Quadros
2023-07-24 15:00 ` [PATCH 5/5] phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config " Swapnil Jakhade
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