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From: Vinod Koul <vkoul@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>,
	 Konrad Dybcio <konrad.dybcio@linaro.org>,
	 Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Neil Armstrong <neil.armstrong@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	 Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Subject: Re: (subset) [PATCH v2 0/7] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock
Date: Fri, 05 Apr 2024 22:39:13 +0530	[thread overview]
Message-ID: <171233695315.304553.592159497575428525.b4-ty@kernel.org> (raw)
In-Reply-To: <20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-0-3ec0a966d52f@linaro.org>


On Fri, 22 Mar 2024 10:42:37 +0100, Neil Armstrong wrote:
> The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
> "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
> is muxed & gated then returned to the PHY as an input.
> 
> Document the clock IDs to select the PIPE clock or the AUX clock,
> also enforce a second clock-output-names and a #clock-cells value of 1
> for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.
> 
> [...]

Applied, thanks!

[1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs
      commit: 72bea132f3680ee51e7ed2cee62892b6f5121909
[2/7] phy: qcom: qmp-pcie: refactor clock register code
      commit: 677b45114b4430a43d2602296617efc4d3f2ab7a
[3/7] phy: qcom: qmp-pcie: register second optional PHY AUX clock
      commit: 583ca9ccfa806605ae1391aafa3f78a8a2cc0b48
[4/7] phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY
      commit: 5cee04a8369049b92d52995e320abff18dfeda44

Best regards,
-- 
~Vinod



-- 
linux-phy mailing list
linux-phy@lists.infradead.org
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      parent reply	other threads:[~2024-04-05 17:09 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-22  9:42 [PATCH v2 0/7] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Neil Armstrong
2024-03-22  9:42 ` [PATCH v2 1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs Neil Armstrong
2024-03-22  9:42 ` [PATCH v2 2/7] phy: qcom: qmp-pcie: refactor clock register code Neil Armstrong
2024-03-22 10:38   ` Dmitry Baryshkov
2024-03-22  9:42 ` [PATCH v2 3/7] phy: qcom: qmp-pcie: register second optional PHY AUX clock Neil Armstrong
2024-03-22 10:41   ` Dmitry Baryshkov
2024-03-22 10:45     ` Neil Armstrong
2024-03-22 11:59       ` Dmitry Baryshkov
2024-03-22  9:42 ` [PATCH v2 4/7] phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY Neil Armstrong
2024-03-22 10:41   ` Dmitry Baryshkov
2024-03-22  9:42 ` [PATCH v2 5/7] arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk Neil Armstrong
2024-03-22  9:42 ` [PATCH v2 6/7] arm64: dts: qcom: sm8550: " Neil Armstrong
2024-03-22  9:42 ` [PATCH v2 7/7] arm64: dts: qcom: sm8650: " Neil Armstrong
2024-04-05 17:09 ` Vinod Koul [this message]

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