From: Adrian Hunter <adrian.hunter@intel.com>
To: Ian Rogers <irogers@google.com>
Cc: linux-kernel@vger.kernel.org,
"Chang S. Bae" <chang.seok.bae@intel.com>,
Masami Hiramatsu <mhiramat@kernel.org>,
Nikolay Borisov <nik.borisov@suse.com>,
Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
linux-perf-users@vger.kernel.org
Subject: Re: [PATCH 05/10] x86/insn: Add support for REX2 prefix to the instruction decoder logic
Date: Fri, 3 May 2024 08:09:57 +0300 [thread overview]
Message-ID: <902c993e-5d4b-4d97-8d48-450dc1ab2b30@intel.com> (raw)
In-Reply-To: <CAP-5=fX4UxekyxkaX8EH8UcAXe-JAdXRTCguWmTJ8mARg64h-Q@mail.gmail.com>
On 2/05/24 21:10, Ian Rogers wrote:
> On Thu, May 2, 2024 at 3:59 AM Adrian Hunter <adrian.hunter@intel.com> wrote:
>>
>> Intel Advanced Performance Extensions (APX) uses a new 2-byte prefix named
>> REX2 to select extended general purpose registers (EGPRs) i.e. r16 to r31.
>>
>> The REX2 prefix is effectively an extended version of the REX prefix.
>>
>> REX2 and EVEX are also used with PUSH/POP instructions to provide a
>> Push-Pop Acceleration (PPX) hint. With PPX hints, a CPU will attempt to
>> fast-forward register data between matching PUSH and POP instructions.
>>
>> REX2 is valid only with opcodes in maps 0 and 1. Similar extension for
>> other maps is provided by the EVEX prefix, covered in a separate patch.
>>
>> Some opcodes in maps 0 and 1 are reserved under REX2. One of these is used
>> for a new 64-bit absolute direct jump instruction JMPABS.
>>
>> Refer to the Intel Advanced Performance Extensions (Intel APX) Architecture
>> Specification for details.
>>
>> Define a code value for the REX2 prefix (INAT_PFX_REX2), and add attribute
>> flags for opcodes reserved under REX2 (INAT_NO_REX2) and to identify
>> opcodes (only JMPABS) that require a mandatory REX2 prefix
>> (INAT_REX2_VARIANT).
>>
>> Amend logic to read the REX2 prefix and get the opcode attribute for the
>> map number (0 or 1) encoded in the REX2 prefix.
>>
>> Amend the awk script that generates the attribute tables from the opcode
>> map, to recognise "REX2" as attribute INAT_PFX_REX2, and "(!REX2)"
>> as attribute INAT_NO_REX2, and "(REX2)" as attribute INAT_REX2_VARIANT.
>>
>> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
>> ---
>> arch/x86/include/asm/inat.h | 11 +++++++++-
>> arch/x86/include/asm/insn.h | 25 ++++++++++++++++++----
>> arch/x86/lib/insn.c | 25 ++++++++++++++++++++++
>> arch/x86/tools/gen-insn-attr-x86.awk | 11 +++++++++-
>> tools/arch/x86/include/asm/inat.h | 11 +++++++++-
>> tools/arch/x86/include/asm/insn.h | 25 ++++++++++++++++++----
>> tools/arch/x86/lib/insn.c | 25 ++++++++++++++++++++++
>> tools/arch/x86/tools/gen-insn-attr-x86.awk | 11 +++++++++-
>> 8 files changed, 132 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/inat.h b/arch/x86/include/asm/inat.h
>> index b56c5741581a..1331bdd39a23 100644
>> --- a/arch/x86/include/asm/inat.h
>> +++ b/arch/x86/include/asm/inat.h
>> @@ -35,6 +35,8 @@
>> #define INAT_PFX_VEX2 13 /* 2-bytes VEX prefix */
>> #define INAT_PFX_VEX3 14 /* 3-bytes VEX prefix */
>> #define INAT_PFX_EVEX 15 /* EVEX prefix */
>> +/* x86-64 REX2 prefix */
>> +#define INAT_PFX_REX2 16 /* 0xD5 */
>>
>> #define INAT_LSTPFX_MAX 3
>> #define INAT_LGCPFX_MAX 11
>> @@ -50,7 +52,7 @@
>>
>> /* Legacy prefix */
>> #define INAT_PFX_OFFS 0
>> -#define INAT_PFX_BITS 4
>> +#define INAT_PFX_BITS 5
>> #define INAT_PFX_MAX ((1 << INAT_PFX_BITS) - 1)
>> #define INAT_PFX_MASK (INAT_PFX_MAX << INAT_PFX_OFFS)
>> /* Escape opcodes */
>> @@ -77,6 +79,8 @@
>> #define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5))
>> #define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6))
>> #define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7))
>> +#define INAT_NO_REX2 (1 << (INAT_FLAG_OFFS + 8))
>> +#define INAT_REX2_VARIANT (1 << (INAT_FLAG_OFFS + 9))
>> /* Attribute making macros for attribute tables */
>> #define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS)
>> #define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS)
>> @@ -128,6 +132,11 @@ static inline int inat_is_rex_prefix(insn_attr_t attr)
>> return (attr & INAT_PFX_MASK) == INAT_PFX_REX;
>> }
>>
>> +static inline int inat_is_rex2_prefix(insn_attr_t attr)
>> +{
>> + return (attr & INAT_PFX_MASK) == INAT_PFX_REX2;
>> +}
>> +
>> static inline int inat_last_prefix_id(insn_attr_t attr)
>> {
>> if ((attr & INAT_PFX_MASK) > INAT_LSTPFX_MAX)
>> diff --git a/arch/x86/include/asm/insn.h b/arch/x86/include/asm/insn.h
>> index 1b29f58f730f..95249ec1f24e 100644
>> --- a/arch/x86/include/asm/insn.h
>> +++ b/arch/x86/include/asm/insn.h
>> @@ -112,10 +112,15 @@ struct insn {
>> #define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
>> #define X86_SIB_BASE(sib) ((sib) & 0x07)
>>
>> -#define X86_REX_W(rex) ((rex) & 8)
>> -#define X86_REX_R(rex) ((rex) & 4)
>> -#define X86_REX_X(rex) ((rex) & 2)
>> -#define X86_REX_B(rex) ((rex) & 1)
>> +#define X86_REX2_M(rex) ((rex) & 0x80) /* REX2 M0 */
>> +#define X86_REX2_R(rex) ((rex) & 0x40) /* REX2 R4 */
>> +#define X86_REX2_X(rex) ((rex) & 0x20) /* REX2 X4 */
>> +#define X86_REX2_B(rex) ((rex) & 0x10) /* REX2 B4 */
>> +
>> +#define X86_REX_W(rex) ((rex) & 8) /* REX or REX2 W */
>> +#define X86_REX_R(rex) ((rex) & 4) /* REX or REX2 R3 */
>> +#define X86_REX_X(rex) ((rex) & 2) /* REX or REX2 X3 */
>> +#define X86_REX_B(rex) ((rex) & 1) /* REX or REX2 B3 */
>>
>> /* VEX bit flags */
>> #define X86_VEX_W(vex) ((vex) & 0x80) /* VEX3 Byte2 */
>> @@ -161,6 +166,18 @@ static inline void insn_get_attribute(struct insn *insn)
>> /* Instruction uses RIP-relative addressing */
>> extern int insn_rip_relative(struct insn *insn);
>>
>> +static inline int insn_is_rex2(struct insn *insn)
>> +{
>> + if (!insn->prefixes.got)
>> + insn_get_prefixes(insn);
>> + return insn->rex_prefix.nbytes == 2;
>
> It'd be nice to capture that a rex2 prefix is by definition 2 bytes.
> Playing devil's advocate, if there were a REX and a REX2 prefix,
> couldn't rex_prefix.nbytes be 3? I'm wondering about other prefix
> combinations that may confuse this logic, maybe someone dreams up
> doing this for say alignment reasons like "rep ret".
REX with REX2 is not allowed.
next prev parent reply other threads:[~2024-05-03 5:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-02 10:58 [PATCH 00/10] perf intel pt: Update instruction decoder for APX and other new instructions Adrian Hunter
2024-05-02 10:58 ` [PATCH 01/10] x86/insn: Add Key Locker instructions to the opcode map Adrian Hunter
2024-05-02 10:58 ` [PATCH 02/10] x86/insn: Fix PUSH instruction in x86 instruction decoder " Adrian Hunter
2024-05-02 13:41 ` Arnaldo Carvalho de Melo
2024-05-02 19:11 ` Adrian Hunter
2024-05-02 10:58 ` [PATCH 03/10] x86/insn: Add VEX versions of VPDPBUSD, VPDPBUSDS, VPDPWSSD and VPDPWSSDS Adrian Hunter
2024-05-02 10:58 ` [PATCH 04/10] x86/insn: Add misc new Intel instructions Adrian Hunter
2024-05-02 10:58 ` [PATCH 05/10] x86/insn: Add support for REX2 prefix to the instruction decoder logic Adrian Hunter
2024-05-02 18:10 ` Ian Rogers
2024-05-03 5:09 ` Adrian Hunter [this message]
2024-05-02 10:58 ` [PATCH 06/10] x86/insn: x86/insn: Add support for REX2 prefix to the instruction decoder opcode map Adrian Hunter
2024-05-02 10:58 ` [PATCH 07/10] x86/insn: Add support for APX EVEX to the instruction decoder logic Adrian Hunter
2024-05-02 10:58 ` [PATCH 08/10] x86/insn: Add support for APX EVEX instructions to the opcode map Adrian Hunter
2024-05-02 10:58 ` [PATCH 09/10] perf intel pt: Add new JMPABS instruction to the Intel PT instruction decoder Adrian Hunter
2024-05-28 18:14 ` Adrian Hunter
2024-05-02 10:58 ` [PATCH 10/10] perf tests: Add APX and other new instructions to x86 instruction decoder test Adrian Hunter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=902c993e-5d4b-4d97-8d48-450dc1ab2b30@intel.com \
--to=adrian.hunter@intel.com \
--cc=acme@kernel.org \
--cc=bp@alien8.de \
--cc=chang.seok.bae@intel.com \
--cc=dave.hansen@linux.intel.com \
--cc=hpa@zytor.com \
--cc=irogers@google.com \
--cc=jolsa@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mhiramat@kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=nik.borisov@suse.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).