From: Tanmay Jagdale <tanmay@marvell.com>
To: <john.g.garry@oracle.com>, <will@kernel.org>,
<james.clark@arm.com>, <mike.leach@linaro.org>,
<leo.yan@linux.dev>, <suzuki.poulose@arm.com>,
<peterz@infradead.org>, <mingo@redhat.com>,
<alexander.shishkin@linux.intel.com>, <jolsa@kernel.org>,
<irogers@google.com>, <adrian.hunter@intel.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<coresight@lists.linaro.org>, <linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <sgoutham@marvell.com>,
<gcherian@marvell.com>, <lcherian@marvell.com>,
Tanmay Jagdale <tanmay@marvell.com>
Subject: [PATCH V2 0/2] Fix Coresight instruction synthesis logic
Date: Thu, 4 Apr 2024 23:37:29 +0530 [thread overview]
Message-ID: <20240404180731.7006-1-tanmay@marvell.com> (raw)
When we use perf to catpure Coresight trace and generate instruction
trace using 'perf script', we get the following output:
# perf record -e cs_etm/@tmc_etr0/ -C 9 taskset -c 9 sleep 1
# perf script --itrace=i1ns --ns -Fcomm,tid,pid,time,cpu,event,ip,sym,addr,symoff,flags,callindent
...
perf 9024/9024 [009] 2690.650470551: instructions: call 0 ffffb305591aed54 coresight_timeout+0x28
perf 9024/9024 [009] 2690.650470551: instructions: call 0 ffffb305591aed58 coresight_timeout+0x2c
perf 9024/9024 [009] 2690.650470551: instructions: call 0 ffffb305591aed5c coresight_timeout+0x30
perf 9024/9024 [009] 2690.650470551: instructions: call 0 ffffb305591aed60 coresight_timeout+0x34
perf 9024/9024 [009] 2690.650470551: instructions: jmp 0 ffffb305591aed7c coresight_timeout+0x50
perf 9024/9024 [009] 2690.650470551: instructions: jmp 0 ffffb305591aed80 coresight_timeout+0x54
perf 9024/9024 [009] 2690.650470551: instructions: jmp 0 ffffb305591aed84 coresight_timeout+0x58
perf 9024/9024 [009] 2690.650470552: instructions: jcc 0 ffffb305591aede4 coresight_timeout+0xb8
perf 9024/9024 [009] 2690.650470552: instructions: jcc 0 ffffb305591aede8 coresight_timeout+0xbc
perf 9024/9024 [009] 2690.650470552: instructions: jcc 0 ffffb305591aedec coresight_timeout+0xc0
perf 9024/9024 [009] 2690.650470552: instructions: jcc 0 ffffb305591aedf0 coresight_timeout+0xc4
perf 9024/9024 [009] 2690.650470557: instructions: call 0 ffffb305591bccec ete_sysreg_read+0x0
perf 9024/9024 [009] 2690.650470557: instructions: call 0 ffffb305591bccf0 ete_sysreg_read+0x4
perf 9024/9024 [009] 2690.650470557: instructions: call 0 ffffb305591bccf4 ete_sysreg_read+0x8
perf 9024/9024 [009] 2690.650470557: instructions: call 0 ffffb305591bccf8 ete_sysreg_read+0xc
perf 9024/9024 [009] 2690.650470557: instructions: call 0 ffffb305591bccfc ete_sysreg_read+0x10
perf 9024/9024 [009] 2690.650470557: instructions: call 0 ffffb305591bcd00 ete_sysreg_read+0x14
This output has the following issues:
1. Non-branch instructions have mnemonics of branch instructions (Column 6)
2. Branch target address is missing (Column 7)
This patch fixes these issues by changing the logic of instruction syntehsis
for the Coresight trace queues.
Output after applying the patch:
...
perf 6111/6111 [008] 457.332794461: instructions: 0 ffffb305591aed54 coresight_timeout+0x28
perf 6111/6111 [008] 457.332794461: instructions: 0 ffffb305591aed58 coresight_timeout+0x2c
perf 6111/6111 [008] 457.332794461: instructions: 0 ffffb305591aed5c coresight_timeout+0x30
perf 6111/6111 [008] 457.332794461: instructions: jmp ffffb305591aed7c ffffb305591aed60 coresight_timeout+0x34
perf 6111/6111 [008] 457.332794461: instructions: 0 ffffb305591aed7c coresight_timeout+0x50
perf 6111/6111 [008] 457.332794461: instructions: 0 ffffb305591aed80 coresight_timeout+0x54
perf 6111/6111 [008] 457.332794461: instructions: jcc ffffb305591aede4 ffffb305591aed84 coresight_timeout+0x58
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591aede4 coresight_timeout+0xb8
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591aede8 coresight_timeout+0xbc
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591aedec coresight_timeout+0xc0
perf 6111/6111 [008] 457.332794462: instructions: call ffffb305591bccec ffffb305591aedf0 coresight_timeout+0xc4
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591bccec ete_sysreg_read+0x0
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591bccf0 ete_sysreg_read+0x4
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591bccf4 ete_sysreg_read+0x8
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591bccf8 ete_sysreg_read+0xc
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591bccfc ete_sysreg_read+0x10
perf 6111/6111 [008] 457.332794462: instructions: 0 ffffb305591bcd00 ete_sysreg_read+0x14
Changes in V2
- Updated commit message of Patch 1
- As discussed in the previous version [1], there were differences in instruction
trace output before and after the patch. The timestamps for the instructions
were not in sync. Added a patch 2 which fixes this issue.
Changes in V1
- https://lkml.org/lkml/2023/6/23/912
[1] https://lkml.org/lkml/2023/6/28/506
Tanmay Jagdale (2):
perf: cs-etm: Fixes in instruction sample synthesis
perf: cs-etm: Store previous timestamp in packet queue
tools/perf/util/cs-etm.c | 49 +++++++++++++++++++++++++++++++---------
tools/perf/util/cs-etm.h | 1 +
2 files changed, 39 insertions(+), 11 deletions(-)
--
2.34.1
next reply other threads:[~2024-04-04 18:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-04 18:07 Tanmay Jagdale [this message]
2024-04-04 18:07 ` [PATCH V2 1/2] perf: cs-etm: Fixes in instruction sample synthesis Tanmay Jagdale
2024-04-04 18:07 ` [PATCH V2 2/2] perf: cs-etm: Store previous timestamp in packet queue Tanmay Jagdale
2024-04-25 18:54 ` [PATCH V2 0/2] Fix Coresight instruction synthesis logic Arnaldo Carvalho de Melo
2024-04-26 15:07 ` James Clark
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