From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Maciej W . Rozycki" <macro@orcam.me.uk>,
"Jonathan Cameron" <Jonathan.Cameron@Huawei.com>,
"Lukas Wunner" <lukas@wunner.de>,
"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: "Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Amit Kucheria" <amitk@kernel.org>,
"Zhang Rui" <rui.zhang@intel.com>,
"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH v6 3/8] PCI: Refactor pcie_update_link_speed()
Date: Thu, 16 May 2024 12:32:17 +0300 [thread overview]
Message-ID: <20240516093222.1684-4-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20240516093222.1684-1-ilpo.jarvinen@linux.intel.com>
pcie_update_link_speed() is passed the Link Status register but not all
callers have that value at hand nor need the value.
Refactor pcie_update_link_speed() to include reading the Link Status
register into pcie_update_link_speed() and create
__pcie_update_link_speed() which can be used by the hotplug code that
has the register value at hand beforehand (and needs the value for
other purposes).
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
drivers/pci/hotplug/pciehp_hpc.c | 2 +-
drivers/pci/pci.h | 7 ++++++-
drivers/pci/probe.c | 12 +++++++-----
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index b1d0a1b3917d..0d818110af6d 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -319,7 +319,7 @@ int pciehp_check_link_status(struct controller *ctrl)
return -1;
}
- pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
+ __pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
if (!found) {
ctrl_info(ctrl, "Slot(%s): No device found\n",
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 48eae81a0a43..664191768395 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -297,7 +297,12 @@ u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
enum pcie_link_width *width);
void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
void pcie_report_downtraining(struct pci_dev *dev);
-void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
+
+static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
+{
+ bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
+}
+void pcie_update_link_speed(struct pci_bus *bus);
/* Single Root I/O Virtualization */
struct pci_sriov {
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 1b08b3f16027..65413d408b3d 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -742,9 +742,13 @@ const char *pci_speed_string(enum pci_bus_speed speed)
}
EXPORT_SYMBOL_GPL(pci_speed_string);
-void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
+void pcie_update_link_speed(struct pci_bus *bus)
{
- bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
+ struct pci_dev *bridge = bus->self;
+ u16 linksta;
+
+ pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
+ __pcie_update_link_speed(bus, linksta);
}
EXPORT_SYMBOL_GPL(pcie_update_link_speed);
@@ -827,15 +831,13 @@ static void pci_set_bus_speed(struct pci_bus *bus)
if (pci_is_pcie(bridge)) {
u32 linkcap;
- u16 linksta;
pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
if (bus->max_bus_speed != PCI_SPEED_UNKNOWN)
bus->supported_speeds = PCI_EXP_LNKCAP2_SLS_2_5GB;
- pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
- pcie_update_link_speed(bus, linksta);
+ pcie_update_link_speed(bus);
}
}
--
2.39.2
next prev parent reply other threads:[~2024-05-16 9:33 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-16 9:32 [PATCH v6 0/8] PCI: Add PCIe bandwidth controller Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 1/8] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 2/8] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2024-05-16 9:32 ` Ilpo Järvinen [this message]
2024-05-16 9:32 ` [PATCH v6 4/8] PCI/quirks: Abstract LBMS seen check into own function Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 5/8] PCI/bwctrl: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 6/8] PCI/bwctrl: Add API to set PCIe Link Speed Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 7/8] thermal: Add PCIe cooling driver Ilpo Järvinen
2024-05-16 9:32 ` [PATCH v6 8/8] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
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