From: Judith Mendez <jm@ti.com>
To: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>,
<linux-mmc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Randolph Sapp <rs@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>
Subject: [PATCH v1 4/5] mmc: sdhci_am654: Add ITAPDLYSEL in sdhci_j721e_4bit_set_clock
Date: Wed, 31 Jan 2024 15:50:43 -0600 [thread overview]
Message-ID: <20240131215044.3163469-5-jm@ti.com> (raw)
In-Reply-To: <20240131215044.3163469-1-jm@ti.com>
Add ITAPDLYSEL to sdhci_j721e_4bit_set_clock function.
This allows to set the correct ITAPDLY for timings that
do not carry out tuning.
Fixes: 1accbced1c32 ("mmc: sdhci_am654: Add Support for 4 bit IP on J721E")
Signed-off-by: Judith Mendez <jm@ti.com>
---
drivers/mmc/host/sdhci_am654.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 5ac82bc70706..f5dc981c470d 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -321,6 +321,7 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
unsigned char timing = host->mmc->ios.timing;
u32 otap_del_sel;
u32 itap_del_ena;
+ u32 itap_del_sel;
u32 mask, val;
/* Setup Output TAP delay */
@@ -329,12 +330,17 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
+ /* Setup Input TAP delay */
itap_del_ena = sdhci_am654->itap_del_ena[timing];
+ itap_del_sel = sdhci_am654->itap_del_sel[timing];
- mask |= ITAPDLYENA_MASK;
- val |= (itap_del_ena << ITAPDLYENA_SHIFT);
+ mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
+ val |= (itap_del_ena << ITAPDLYENA_SHIFT) | (itap_del_sel << ITAPDLYSEL_SHIFT);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
+ 1 << ITAPCHGWIN_SHIFT);
regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
sdhci_am654->clkbuf_sel);
--
2.34.1
next prev parent reply other threads:[~2024-01-31 21:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-31 21:50 [PATCH v1 0/5] Add tuning algorithm for delay chain Judith Mendez
2024-01-31 21:50 ` [PATCH v1 1/5] mmc: sdhci_am654: " Judith Mendez
2024-02-01 19:24 ` Andrew Davis
2024-01-31 21:50 ` [PATCH v1 2/5] mmc: sdhci_am654: Write ITAPDLY for DDR52 timing Judith Mendez
2024-02-01 19:36 ` Andrew Davis
2024-02-06 21:58 ` Judith Mendez
2024-02-06 22:10 ` Judith Mendez
2024-01-31 21:50 ` [PATCH v1 3/5] mmc: sdhci_am654: Add missing OTAP/ITAP enable Judith Mendez
2024-02-01 19:46 ` Andrew Davis
2024-02-06 22:00 ` Judith Mendez
2024-02-06 22:16 ` Andrew Davis
2024-01-31 21:50 ` Judith Mendez [this message]
2024-02-01 19:57 ` [PATCH v1 4/5] mmc: sdhci_am654: Add ITAPDLYSEL in sdhci_j721e_4bit_set_clock Andrew Davis
2024-02-01 21:52 ` Judith Mendez
2024-02-02 4:42 ` Vignesh Raghavendra
2024-01-31 21:50 ` [PATCH v1 5/5] mmc: sdhci_am654: Fix ITAPDLY for HS400 timing Judith Mendez
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