From: Florian Fainelli <florian.fainelli@broadcom.com>
To: Christian Marangi <ansuelsmth@gmail.com>,
Conor Dooley <conor@kernel.org>
Cc: "Hauke Mehrtens" <hauke@hauke-m.de>,
"Rafał Miłecki" <zajec5@gmail.com>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Broadcom internal kernel review list"
<bcm-kernel-feedback-list@broadcom.com>,
linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
Date: Thu, 9 May 2024 09:01:56 -0700 [thread overview]
Message-ID: <6828e1da-65c5-43a5-9b5c-0c86f4e523ea@broadcom.com> (raw)
In-Reply-To: <663bb3bf.050a0220.38dcc.9b82@mx.google.com>
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On 5/8/24 10:17, Christian Marangi wrote:
> On Wed, May 08, 2024 at 06:14:34PM +0100, Conor Dooley wrote:
>> On Wed, May 08, 2024 at 07:07:18PM +0200, Christian Marangi wrote:
>>> Document brcm,bmips-cbr-reg property.
>>>
>>> Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
>>> if called from TP1. The CBR address is always the same on the SoC
>>> hence it can be provided in DT to handle broken case where bootloader
>>> doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
>>>
>>> Usage of this property is to give an address also in these broken
>>> configuration/bootloader.
>>>
>>> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
>>> ---
>>> .../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++
>>> 1 file changed, 23 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>>> index 975945ca2888..77f73ab48c11 100644
>>> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>>> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>>> @@ -55,6 +55,15 @@ properties:
>>> under the "cpus" node.
>>> $ref: /schemas/types.yaml#/definitions/uint32
>>>
>>> + brcm,bmips-cbr-reg:
>>> + description: Reference address of the CBR.
>>
>> Pretty sure that Rob commented last time that there's no definition
>> anywhere here of CBR, but I don't see either a response to him or an
>> explanation in v3 as to what CBR means.
>>
>
> Sorry I missed it.
FWIW, CBR mean Core Base Register. It is accessed via co-processor 0,
register 22, selector 6 using the MIPS processor's way of adding custom
co-processor registers.
--
Florian
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next prev parent reply other threads:[~2024-05-09 16:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-08 17:07 [PATCH v3 0/4] mips: bmips: improve handling of RAC and CBR addr Christian Marangi
2024-05-08 17:07 ` [PATCH v3 1/4] mips: bmips: rework and cache CBR addr handling Christian Marangi
2024-05-08 17:07 ` [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Christian Marangi
2024-05-08 17:14 ` Conor Dooley
2024-05-08 17:17 ` Christian Marangi
2024-05-09 16:01 ` Florian Fainelli [this message]
2024-05-08 17:07 ` [PATCH v3 3/4] mips: bmips: setup: make CBR address configurable Christian Marangi
2024-05-08 17:07 ` [PATCH v3 4/4] mips: bmips: enable RAC on BMIPS4350 Christian Marangi
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