From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Serge Semin <fancer.lancer@gmail.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH 7/7] clocksource: mips-gic-timer: Correct sched_clock width
Date: Sat, 11 May 2024 17:00:14 +0100 [thread overview]
Message-ID: <20240511-mips-clks-v1-7-ddb4a10ee9f9@flygoat.com> (raw)
In-Reply-To: <20240511-mips-clks-v1-0-ddb4a10ee9f9@flygoat.com>
Counter width of GIC is configurable and can be read from a
register.
Use width value from the register for sched_clock.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
drivers/clocksource/mips-gic-timer.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 67498dc9c5a5..47143e49fc44 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -19,6 +19,7 @@
static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
static int gic_timer_irq;
static unsigned int gic_frequency;
+static unsigned int gic_count_width;
static bool __read_mostly gic_clock_unstable;
static void gic_clocksource_unstable(char *reason);
@@ -186,15 +187,14 @@ static void gic_clocksource_unstable(char *reason)
static int __init __gic_clocksource_init(void)
{
- unsigned int count_width;
int ret;
/* Set clocksource mask. */
- count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
- count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
- count_width *= 4;
- count_width += 32;
- gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
+ gic_count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
+ gic_count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
+ gic_count_width *= 4;
+ gic_count_width += 32;
+ gic_clocksource.mask = CLOCKSOURCE_MASK(gic_count_width);
/* Calculate a somewhat reasonable rating value. */
if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ))
@@ -264,7 +264,7 @@ static int __init gic_clocksource_of_init(struct device_node *node)
if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
sched_clock_register(mips_cm_is64 ?
gic_read_count_64 : gic_read_count_2x32,
- 64, gic_frequency);
+ gic_count_width, gic_frequency);
}
return 0;
--
2.34.1
next prev parent reply other threads:[~2024-05-11 16:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-11 16:00 [PATCH 0/7] MIPS: clocksource cumulative enhancements Jiaxun Yang
2024-05-11 16:00 ` [PATCH 1/7] MIPS: csrc-r4k: Refine rating computation Jiaxun Yang
2024-06-01 22:23 ` Maciej W. Rozycki
2024-05-11 16:00 ` [PATCH 2/7] MIPS: csrc-r4k: Apply verification clocksource flags Jiaxun Yang
2024-05-11 16:00 ` [PATCH 3/7] MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if 64BIT Jiaxun Yang
2024-06-01 22:30 ` Maciej W. Rozycki
2024-06-04 14:51 ` Jiaxun Yang
2024-05-11 16:00 ` [PATCH 4/7] MIPS: csrc-r4k: Don't register as sched_clock if unfit Jiaxun Yang
2024-05-11 16:00 ` [PATCH 5/7] MIPS: sync-r4k: Rework based on x86 tsc_sync Jiaxun Yang
2024-05-11 16:00 ` [PATCH 6/7] clocksource: mips-gic-timer: Refine rating computation Jiaxun Yang
2024-05-11 16:00 ` Jiaxun Yang [this message]
2024-05-27 12:24 ` [PATCH 7/7] clocksource: mips-gic-timer: Correct sched_clock width Philippe Mathieu-Daudé
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