From: Conor Dooley <conor@kernel.org>
To: Christian Marangi <ansuelsmth@gmail.com>
Cc: "Hauke Mehrtens" <hauke@hauke-m.de>,
"Rafał Miłecki" <zajec5@gmail.com>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Florian Fainelli" <florian.fainelli@broadcom.com>,
"Broadcom internal kernel review list"
<bcm-kernel-feedback-list@broadcom.com>,
linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
Date: Sat, 11 May 2024 13:52:16 +0100 [thread overview]
Message-ID: <20240511-headset-self-dc2501b38a71@spud> (raw)
In-Reply-To: <20240509204750.1538-3-ansuelsmth@gmail.com>
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On Thu, May 09, 2024 at 10:47:46PM +0200, Christian Marangi wrote:
> Document brcm,bmips-cbr-reg property.
>
> Some SoC suffer from a BUG where CBR(Core Base Register)
> address might badly/never inizialized by the Bootloader or
> reaching it from co-processor registers if the system
> boots from secondary CPU results in invalid address.
>
> The CBR address is always the same on the SoC.
>
> Usage of this property is to give an address also in these broken
> configuration/bootloader.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> .../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> index 975945ca2888..6b961b62aff2 100644
> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> @@ -55,6 +55,16 @@ properties:
> under the "cpus" node.
> $ref: /schemas/types.yaml#/definitions/uint32
>
> + brcm,bmips-cbr-reg:
> + description: Reference address of the CBR.
> + Some SoC suffer from a BUG where CBR(Core Base Register)
> + address might badly/never inizialized by the Bootloader or
"be badly or never initialized"
> + reaching it from co-processor registers if the system
"reading"?
Otherwise,
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
> + boots from secondary CPU results in invalid address.
> + The CBR address is always the same on the SoC hence it
> + can be provided in DT to handle these broken case.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> patternProperties:
> "^cpu@[0-9]$":
> type: object
> @@ -64,6 +74,20 @@ properties:
> required:
> - mips-hpt-frequency
>
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - brcm,bcm6358
> + - brcm,bcm6368
> +
> +then:
> + properties:
> + cpus:
> + required:
> + - brcm,bmips-cbr-reg
> +
> additionalProperties: true
>
> examples:
> --
> 2.43.0
>
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next prev parent reply other threads:[~2024-05-11 12:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-09 20:47 [PATCH v4 0/4] mips: bmips: improve handling of RAC and CBR addr Christian Marangi
2024-05-09 20:47 ` [PATCH v4 1/4] mips: bmips: rework and cache CBR addr handling Christian Marangi
2024-05-09 21:38 ` Florian Fainelli
2024-05-09 20:47 ` [PATCH v4 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Christian Marangi
2024-05-11 12:52 ` Conor Dooley [this message]
2024-05-09 20:47 ` [PATCH v4 3/4] mips: bmips: setup: make CBR address configurable Christian Marangi
2024-05-09 21:38 ` Florian Fainelli
2024-05-09 20:47 ` [PATCH v4 4/4] mips: bmips: enable RAC on BMIPS4350 Christian Marangi
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