From: Ivan Bornyakov <brnkv.i1@gmail.com>
To: Nas Chung <nas.chung@chipsnmedia.com>,
Jackson Lee <jackson.lee@chipsnmedia.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Sebastian Fricke <sebastian.fricke@collabora.com>
Cc: Ivan Bornyakov <brnkv.i1@gmail.com>,
linux-media@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 3/5] media: chips-media: wave5: separate irq setup routine
Date: Mon, 15 Apr 2024 13:07:21 +0300 [thread overview]
Message-ID: <20240415100726.19911-4-brnkv.i1@gmail.com> (raw)
In-Reply-To: <20240415100726.19911-1-brnkv.i1@gmail.com>
Implement a separate setup routine for interrupts to reduce code
duplication. Also enable interrupts based on vpu_attr->support_encoders
and vpu_attr->support_decoders fields to facilitate support for other
Wave5xx IPs, because not all of them are both encoders and decoders.
Signed-off-by: Ivan Bornyakov <brnkv.i1@gmail.com>
---
.../platform/chips-media/wave5/wave5-hw.c | 53 +++++++++----------
1 file changed, 24 insertions(+), 29 deletions(-)
diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
index 2d82791f575e..cdd0a0948a94 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
@@ -299,6 +299,27 @@ static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *ins
return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL);
}
+static void setup_wave5_interrupts(struct vpu_device *vpu_dev)
+{
+ u32 reg_val = 0;
+
+ if (vpu_dev->attr.support_encoders) {
+ /* Encoder interrupt */
+ reg_val |= BIT(INT_WAVE5_ENC_SET_PARAM);
+ reg_val |= BIT(INT_WAVE5_ENC_PIC);
+ reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
+ }
+
+ if (vpu_dev->attr.support_decoders) {
+ /* Decoder interrupt */
+ reg_val |= BIT(INT_WAVE5_INIT_SEQ);
+ reg_val |= BIT(INT_WAVE5_DEC_PIC);
+ reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
+ }
+
+ return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
+}
+
static int setup_wave5_properties(struct device *dev)
{
struct vpu_device *vpu_dev = dev_get_drvdata(dev);
@@ -340,6 +361,8 @@ static int setup_wave5_properties(struct device *dev)
p_attr->support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, hw_config_def0);
p_attr->support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, hw_config_def0);
+ setup_wave5_interrupts(vpu_dev);
+
return 0;
}
@@ -417,16 +440,6 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size)
wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
- /* Encoder interrupt */
- reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
- reg_val |= BIT(INT_WAVE5_ENC_PIC);
- reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
- /* Decoder interrupt */
- reg_val |= BIT(INT_WAVE5_INIT_SEQ);
- reg_val |= BIT(INT_WAVE5_DEC_PIC);
- reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
- vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
-
reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {
reg_val = ((WAVE5_PROC_AXI_ID << 28) |
@@ -1034,16 +1047,6 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size)
wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
- /* Encoder interrupt */
- reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
- reg_val |= BIT(INT_WAVE5_ENC_PIC);
- reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
- /* Decoder interrupt */
- reg_val |= BIT(INT_WAVE5_INIT_SEQ);
- reg_val |= BIT(INT_WAVE5_DEC_PIC);
- reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
- vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
-
reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {
reg_val = ((WAVE5_PROC_AXI_ID << 28) |
@@ -1134,15 +1137,7 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin
wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
- /* Encoder interrupt */
- reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
- reg_val |= BIT(INT_WAVE5_ENC_PIC);
- reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
- /* Decoder interrupt */
- reg_val |= BIT(INT_WAVE5_INIT_SEQ);
- reg_val |= BIT(INT_WAVE5_DEC_PIC);
- reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
- vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
+ setup_wave5_interrupts(vpu_dev);
reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {
--
2.44.0
next prev parent reply other threads:[~2024-04-15 10:07 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 10:07 [PATCH v4 0/5] Wave515 decoder IP support Ivan Bornyakov
2024-04-15 10:07 ` [PATCH v4 1/5] media: chips-media: wave5: support decoding HEVC Main10 profile Ivan Bornyakov
2024-04-15 10:07 ` [PATCH v4 2/5] media: chips-media: wave5: support reset lines Ivan Bornyakov
2024-04-15 10:07 ` Ivan Bornyakov [this message]
2024-04-15 10:07 ` [PATCH v4 4/5] media: chips-media: wave5: drop "sram-size" DT prop Ivan Bornyakov
2024-04-15 10:07 ` [PATCH v4 5/5] media: chips-media: wave5: support Wave515 decoder Ivan Bornyakov
2024-04-15 12:49 ` [PATCH v4 0/5] Wave515 decoder IP support Sebastian Fricke
2024-04-15 13:07 ` Ivan Bornyakov
2024-05-02 6:40 ` Ivan Bornyakov
2024-05-03 15:07 ` Sebastian Fricke
2024-05-24 9:09 ` Ivan Bornyakov
2024-05-24 10:19 ` Sebastian Fricke
2024-05-25 10:09 ` Ivan Bornyakov
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