From: Charlie Jenkins <charlie@rivosinc.com>
To: Alejandro Colomar <alx@kernel.org>
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>,
linux-man@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>
Subject: [PATCH] prctl.2: Add PR_RISCV_SET_ICACHE_FLUSH_CTX
Date: Wed, 24 Jan 2024 18:59:04 -0800 [thread overview]
Message-ID: <20240124-fencei_prctl-v1-1-0bddafcef331@rivosinc.com> (raw)
I have proposed and documented the PR_RISCV_SET_ICACHE_FLUSH_CTX flag
for prctl(2) to LKML. It has been reviewed and is expected to land
during the Linux version 6.9 merge window. This adds the relevant
documentation from that patch.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
I have proposed and documented the PR_RISCV_SET_ICACHE_FLUSH_CTX
flag for prctl(2) to LKML. It has been reviewed and is expected to land
during the Linux version 6.9 merge window.
---
man2/prctl.2 | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/man2/prctl.2 b/man2/prctl.2
index f1604a7cb..2889a7195 100644
--- a/man2/prctl.2
+++ b/man2/prctl.2
@@ -1147,6 +1147,64 @@ For further information, see the kernel source file
(or
.I Documentation/security/Yama.txt
before Linux 4.13).
+.\" prctl PR_RISCV_SET_ICACHE_FLUSH_CTX
+.TP
+.BR PR_RISCV_SET_ICACHE_FLUSH_CTX " (since Linux 6.9, RISC-V only)"
+Enable/disable icache flushing instructions in userspace. The ctx and the
+scope can be provided using
+.IR arg2
+and
+.IR arg3
+respectively. When scope is set to
+.B PR_RISCV_SCOPE_PER_PROCESS ,
+all threads in the process are permitted to emit icache flushing
+instructions. Whenever any thread in the process is migrated, the
+corresponding hart's icache will be guaranteed to be consistent with
+instruction storage. Note this does not enforce any guarantees outside of
+migration. If a thread modifies an instruction that another thread may
+attempt to execute, the other thread must still emit an icache flushing
+instruction before attempting to execute the potentially modified
+instruction. This must be performed by the userspace program.
+.IP
+In per-thread context (eg. scope is set to
+.B PR_RISCV_SCOPE_PER_THREAD )
+, only the thread calling this function is permitted to emit icache
+flushing instructions. When the thread is migrated, the corresponding
+hart's icache will be guaranteed to be consistent with instruction storage.
+.IP
+On kernels configured without SMP, this function is a nop as migrations
+across harts will not occur.
+.IP
+The following values for
+.IR arg2
+can be specified:
+.RS
+.TP
+.BR PR_RISCV_CTX_SW_FENCEI_ON " (since Linux 6.9)"
+Allow fence.i in userspace.
+.TP
+.BR PR_RISCV_CTX_SW_FENCEI_OFF " (since Linux 6.9)"
+Disallow fence.i in userspace. All threads in a process will be affected
+when scope is set to
+.B PR_RISCV_SCOPE_PER_PROCESS .
+Therefore, caution must be taken -- only use this flag when you can
+guarantee that no thread in the process will emit fence.i from this point
+onward.
+.RE
+.IP
+The following values for
+.IR arg3
+can be specified:
+.RS
+.TP
+.BR PR_RISCV_SCOPE_PER_PROCESS " (since Linux 6.9)"
+Ensure the icache of any thread in this process is coherent with
+instruction storage upon migration.
+.TP
+.BR PR_RISCV_SCOPE_PER_THREAD " (since Linux 6.9)"
+Ensure the icache of the current thread is coherent with instruction
+storage upon migration.
+.RE
.\" prctl PR_SET_SECCOMP
.TP
.BR PR_SET_SECCOMP " (since Linux 2.6.23)"
---
base-commit: a81e893f2b9316869e6098c3a079c30a48158092
change-id: 20240124-fencei_prctl-c24da2643379
Best regards,
--
Charlie Jenkins <charlie@rivosinc.com>
next reply other threads:[~2024-01-25 3:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-25 2:59 Charlie Jenkins [this message]
2024-02-11 18:38 ` [PATCH] prctl.2: Add PR_RISCV_SET_ICACHE_FLUSH_CTX Alejandro Colomar
2024-02-13 1:36 ` Charlie Jenkins
2024-02-13 12:03 ` Alejandro Colomar
2024-02-13 14:32 ` G. Branden Robinson
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