From: Vasant Hegde <vasant.hegde@amd.com>
To: <iommu@lists.linux.dev>, <joro@8bytes.org>
Cc: <suravee.suthikulpanit@amd.com>, <wei.huang2@amd.com>,
<jsnitsel@redhat.com>, <jgg@ziepe.ca>,
Vasant Hegde <vasant.hegde@amd.com>
Subject: [PATCH v6 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF
Date: Fri, 9 Feb 2024 11:29:15 +0000 [thread overview]
Message-ID: <20240209112930.63663-1-vasant.hegde@amd.com> (raw)
This is part 4 of the 4-part series to introduce Share Virtual Address
(SVA) support for devices, which can support PCI ATS, PASID and PRI
capabilities. These devices are referred to as SVA-capable devices in
this series.
It contains the following enhancements:
* Patch 1 - 3:
Rename, add support to enable/disable features, update DTE etc.
* Patch 4 - 12:
Add IOPF support
* Patch 13 - 15:
Introduce SVA support
This patch series is based on top of SVA Part 3 v7.
https://lore.kernel.org/linux-iommu/20240205115615.6053-1-vasant.hegde@amd.com/T/#t
Also depends on :
1) Baolu's IOPF improvement v12
https://lore.kernel.org/linux-iommu/c918825d-ad74-4b1d-abcc-31c3f3ea4620@linux.intel.com/T/#t
This is also available at github :
https://github.com/AMDESE/linux/tree/iommu_sva_part4_v6_v6.8_rc2
Thanks everyone who reviewed previous version and provided valuable feedbacks.
Changes from v5 -> v6:
- Rebased on top of SVA Part3 v7
- Reorganized, added few patches
- Patch to track per device max PASIDs
- Patch to setup GCR3 table for SVA capable domain
- Patch to enable PASID/PRI only when domain is capable of PRI support
- Dropped below patches as they are not needed anymore
- iommu/amd: Add GCR3 [un]initialization function
- iommu/amd: Add support for add/remove device for IOPF
- Rework sev[/remove_dev]_dev_pasid() functions
- Dropped late gcr3 setup patch
v5: https://lore.kernel.org/linux-iommu/20240118073339.6978-1-vasant.hegde@amd.com/T/#t
Changes from v4 -> v5:
- Rebased on top of v6.7-rc8 + SVA Part3 patches
- Few minor improvements like renaming structure name for better, introducing macros, etc
V4: https://lore.kernel.org/linux-iommu/20231221111558.64652-1-vasant.hegde@amd.com/
Changes from v3 -> v4:
- Moved amd_iommu_dev_update_dte() after set/clear_dte() so that we can avoid
forward declaration
- Dropped "iommu/amd: Do not override PASID entry in GCR3 table"
- Added patch to fix PPR interrupt processing logic
- Renamed enable_iommus_v2() -> enable_iommus_ppr()
- Added ops->domain_alloc_sva()
- Added domain_alloc_sva() support and reorganize SVA patches
- In error path iommu_call_iopf_notifier() calls amd_iommu_complete_ppr()
instead of amd_iommu_page_response()
v3: https://lore.kernel.org/linux-iommu/20231016104351.5749-1-vasant.hegde@amd.com/T/#t
Changes from v2 -> v3:
- Rename sva.c -> pasid.c
- Changed amd_iommu_sva_supported() -> amd_iommu_pasid_supported()
- Added patch to update/flush DTE
- Rework part of SVA support
- Move IOPF enablement to PASID bind time
v2: https://lore.kernel.org/linux-iommu/20230911121046.1025732-1-vasant.hegde@amd.com/T/#u
Changes from v1 -> v2:
- Added new patch to fix PASID override issue in GCR3 table
- Complete rework of SVA code on top of Tina's SVA series.
- Rework SVA enable code
- Reworked IOPF handler code on top of Baolu's IOPF improvement series.
v1: https://lore.kernel.org/linux-iommu/20230823140415.729050-1-vasant.hegde@amd.com/T/#t
Thank you,
Vasant / Suravee
Jason Gunthorpe (1):
iommu: Add ops->domain_alloc_sva()
Suravee Suthikulpanit (3):
iommu/amd: Move PPR-related functions into ppr.c
iommu/amd: Define per-IOMMU iopf_queue
iommu/amd: Add support for page response
Vasant Hegde (9):
iommu/amd: Rename amd_iommu_v2_supported() as
amd_iommu_pasid_supported()
iommu/amd: Introduce per device DTE update function
iommu/amd: Fix PPR interrupt processing logic
iommu/amd: Introduce iommu_dev_data.max_pasids
iommu/amd: Setup GCR3 table in advance if domain is SVA capable
iommu/amd: Enable PCI features based on attached domain capability
iommu/amd: Add support for enable/disable IOPF
iommu/amd: Initial SVA support for AMD IOMMU
iommu/amd: Add SVA domain support
Wei Huang (2):
iommu/amd: Add support for enabling/disabling IOMMU features
iommu/amd: Add IO page fault notifier handler
drivers/iommu/amd/Kconfig | 2 +
drivers/iommu/amd/Makefile | 2 +-
drivers/iommu/amd/amd_iommu.h | 50 ++++-
drivers/iommu/amd/amd_iommu_types.h | 33 ++++
drivers/iommu/amd/init.c | 85 +++------
drivers/iommu/amd/iommu.c | 284 ++++++++++++++++++----------
drivers/iommu/amd/pasid.c | 202 ++++++++++++++++++++
drivers/iommu/amd/ppr.c | 284 ++++++++++++++++++++++++++++
drivers/iommu/iommu-sva.c | 16 +-
include/linux/iommu.h | 3 +
10 files changed, 788 insertions(+), 173 deletions(-)
create mode 100644 drivers/iommu/amd/pasid.c
create mode 100644 drivers/iommu/amd/ppr.c
--
2.31.1
next reply other threads:[~2024-02-09 11:29 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-09 11:29 Vasant Hegde [this message]
2024-02-09 11:29 ` [PATCH v6 01/15] iommu/amd: Rename amd_iommu_v2_supported() as amd_iommu_pasid_supported() Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 02/15] iommu/amd: Introduce per device DTE update function Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 03/15] iommu/amd: Add support for enabling/disabling IOMMU features Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 04/15] iommu/amd: Move PPR-related functions into ppr.c Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 05/15] iommu/amd: Fix PPR interrupt processing logic Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 06/15] iommu/amd: Introduce iommu_dev_data.max_pasids Vasant Hegde
2024-03-04 23:46 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 07/15] iommu/amd: Setup GCR3 table in advance if domain is SVA capable Vasant Hegde
2024-03-05 0:11 ` Jason Gunthorpe
2024-03-11 11:20 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 08/15] iommu/amd: Enable PCI features based on attached domain capability Vasant Hegde
2024-03-05 0:32 ` Jason Gunthorpe
2024-03-05 15:10 ` Vasant Hegde
2024-03-05 16:01 ` Jason Gunthorpe
2024-03-11 10:02 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 09/15] iommu/amd: Define per-IOMMU iopf_queue Vasant Hegde
2024-03-05 0:33 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 10/15] iommu/amd: Add support for page response Vasant Hegde
2024-03-05 0:35 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 11/15] iommu/amd: Add IO page fault notifier handler Vasant Hegde
2024-03-05 0:40 ` Jason Gunthorpe
2024-03-11 11:00 ` Vasant Hegde
2024-03-19 17:54 ` Jason Gunthorpe
2024-02-09 11:29 ` [PATCH v6 12/15] iommu/amd: Add support for enable/disable IOPF Vasant Hegde
2024-03-05 0:42 ` Jason Gunthorpe
2024-03-05 15:21 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 13/15] iommu/amd: Initial SVA support for AMD IOMMU Vasant Hegde
2024-03-05 0:50 ` Jason Gunthorpe
2024-03-11 11:11 ` Vasant Hegde
2024-03-19 17:56 ` Jason Gunthorpe
2024-03-27 6:15 ` Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 14/15] iommu: Add ops->domain_alloc_sva() Vasant Hegde
2024-02-09 11:29 ` [PATCH v6 15/15] iommu/amd: Add SVA domain support Vasant Hegde
2024-03-05 0:52 ` [PATCH v6 00/15] iommu/amd: SVA Support (Part 4) - SVA and IOPF Jason Gunthorpe
2024-03-05 14:59 ` Vasant Hegde
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240209112930.63663-1-vasant.hegde@amd.com \
--to=vasant.hegde@amd.com \
--cc=iommu@lists.linux.dev \
--cc=jgg@ziepe.ca \
--cc=joro@8bytes.org \
--cc=jsnitsel@redhat.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=wei.huang2@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).