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From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>
Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org,
	Nicolas Boichat <drinkcat@chromium.org>,
	srv_heupstream@mediatek.com,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	linux-kernel@vger.kernel.org, Evan Green <evgreen@chromium.org>,
	Tomasz Figa <tfiga@google.com>,
	iommu@lists.linux-foundation.org,
	linux-mediatek@lists.infradead.org, chao.hao@mediatek.com,
	anan.sun@mediatek.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 04/24] iommu/mediatek: Adapt sharing and non-sharing pgtable case
Date: Wed, 30 Jun 2021 10:34:44 +0800	[thread overview]
Message-ID: <20210630023504.18177-5-yong.wu@mediatek.com> (raw)
In-Reply-To: <20210630023504.18177-1-yong.wu@mediatek.com>

In previous mt2712, Both are MM IOMMU, they will share pgtable.
But in the later SoC, another is infra IOMMU, there is no reason to
share pgtable between MM with INFRA IOMMU. This patch try to manage
the two case(sharing or non-sharing pgtable).

Currently we use for_each_m4u to loop the 2 HW. I add the list_head into
this macro.
In the sharing pgtable case, the list_head is the global "m4ulist".
In the non-sharing pgtable case, the list_head is hw_list_head which is a
variable in the "data". then for_each_m4u will only loop itself.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 47 ++++++++++++++++++++++-----------------
 drivers/iommu/mtk_iommu.h |  3 +++
 2 files changed, 29 insertions(+), 21 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 013dbcc87d49..4689b65fdb03 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -120,6 +120,7 @@
 #define WR_THROT_EN			BIT(6)
 #define HAS_LEGACY_IVRP_PADDR		BIT(7)
 #define IOVA_34_EN			BIT(8)
+#define SHARE_PGTABLE			BIT(9) /* 2 HW share pgtable */
 
 #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
 		((((pdata)->flags) & (_x)) == (_x))
@@ -167,7 +168,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);
 
 static LIST_HEAD(m4ulist);	/* List all the M4U HWs */
 
-#define for_each_m4u(data)	list_for_each_entry(data, &m4ulist, list)
+#define for_each_m4u(data, head)  list_for_each_entry(data, head, list)
 
 struct mtk_iommu_iova_region {
 	dma_addr_t		iova_base;
@@ -188,21 +189,10 @@ static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
 	#endif
 };
 
-/*
- * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
- * for the performance.
- *
- * Here always return the mtk_iommu_data of the first probed M4U where the
- * iommu domain information is recorded.
- */
-static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
+/* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
+static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist)
 {
-	struct mtk_iommu_data *data;
-
-	for_each_m4u(data)
-		return data;
-
-	return NULL;
+	return list_first_entry(hwlist, struct mtk_iommu_data, list);
 }
 
 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
@@ -212,7 +202,9 @@ static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 
 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
 {
-	for_each_m4u(data) {
+	struct list_head *head = data->hw_list;
+
+	for_each_m4u(data, head) {
 		if (pm_runtime_get_if_in_use(data->dev) <= 0)
 			continue;
 
@@ -229,12 +221,13 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 					   size_t granule,
 					   struct mtk_iommu_data *data)
 {
+	struct list_head *head = data->hw_list;
 	bool has_pm = !!data->dev->pm_domain;
 	unsigned long flags;
 	int ret;
 	u32 tmp;
 
-	for_each_m4u(data) {
+	for_each_m4u(data, head) {
 		if (has_pm) {
 			if (pm_runtime_get_if_in_use(data->dev) <= 0)
 				continue;
@@ -390,13 +383,14 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
 				     unsigned int domid)
 {
 	const struct mtk_iommu_iova_region *region;
+	struct list_head *head = data->hw_list;
 	struct mtk_iommu_data *tmpdata;
 
 	/*
 	 * Loop to find if there is already the exist domain.
 	 * Use it when 2 iommu HWs share the pgtable.
 	 */
-	for_each_m4u(tmpdata) {
+	for_each_m4u(tmpdata, head) {
 		if (!tmpdata->m4u_dom)
 			continue;
 
@@ -600,10 +594,12 @@ static void mtk_iommu_release_device(struct device *dev)
 
 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
 {
-	struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
+	struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data;
+	struct list_head *hw_list = c_data->hw_list;
 	struct iommu_group *group;
 	int domid;
 
+	data = mtk_iommu_get_frst_data(hw_list);
 	if (!data)
 		return ERR_PTR(-ENODEV);
 
@@ -904,7 +900,15 @@ static int mtk_iommu_probe(struct platform_device *pdev)
 		goto out_sysfs_remove;
 
 	spin_lock_init(&data->tlb_lock);
-	list_add_tail(&data->list, &m4ulist);
+
+	if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
+		list_add_tail(&data->list, data->plat_data->hw_list);
+		data->hw_list = data->plat_data->hw_list;
+	} else {
+		INIT_LIST_HEAD(&data->hw_list_head);
+		list_add_tail(&data->list, &data->hw_list_head);
+		data->hw_list = &data->hw_list_head;
+	}
 
 	if (!iommu_present(&platform_bus_type)) {
 		ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
@@ -1008,7 +1012,8 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
 
 static const struct mtk_iommu_plat_data mt2712_data = {
 	.m4u_plat     = M4U_MT2712,
-	.flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
+	.flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE,
+	.hw_list      = &m4ulist,
 	.inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
 	.iova_region  = single_domain,
 	.iova_region_nr = ARRAY_SIZE(single_domain),
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index f81fa8862ed0..a41334b12b20 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -55,6 +55,7 @@ struct mtk_iommu_plat_data {
 	u32                 flags;
 	u32                 inv_sel_reg;
 
+	struct list_head			*hw_list;
 	unsigned int				iova_region_nr;
 	const struct mtk_iommu_iova_region	*iova_region;
 	unsigned char       larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
@@ -80,6 +81,8 @@ struct mtk_iommu_data {
 
 	struct dma_iommu_mapping	*mapping; /* For mtk_iommu_v1.c */
 
+	struct list_head		*hw_list;
+	struct list_head		hw_list_head;
 	struct list_head		list;
 	struct mtk_smi_larb_iommu	larb_imu[MTK_LARB_NR_MAX];
 };
-- 
2.18.0

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  parent reply	other threads:[~2021-06-30  2:36 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-30  2:34 [PATCH 00/24] MT8195 IOMMU SUPPORT Yong Wu
2021-06-30  2:34 ` [PATCH 01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2021-06-30  6:26   ` Krzysztof Kozlowski
2021-06-30  7:30     ` Yong Wu
2021-07-14 21:11   ` Rob Herring
2021-06-30  2:34 ` [PATCH 02/24] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Yong Wu
2021-06-30  6:27   ` Krzysztof Kozlowski
2021-07-14 21:14   ` Rob Herring
2021-06-30  2:34 ` [PATCH 03/24] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2021-06-30  2:34 ` Yong Wu [this message]
2021-06-30  2:34 ` [PATCH 05/24] iommu/mediatek: Add 12G~16G support for mult domain Yong Wu
2021-06-30  2:34 ` [PATCH 06/24] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2021-06-30  2:34 ` [PATCH 07/24] iommu/mediatek: Add flag NON_STD_AXI Yong Wu
2021-06-30  2:34 ` [PATCH 08/24] iommu/mediatek: Remove for_each_m4u in tlb_sync_all Yong Wu
2021-06-30  2:34 ` [PATCH 09/24] iommu/mediatek: Always pm_runtime_get while tlb flush Yong Wu
2021-06-30  2:34 ` [PATCH 10/24] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2021-06-30  2:34 ` [PATCH 11/24] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2021-06-30  2:34 ` [PATCH 12/24] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2021-06-30  2:34 ` [PATCH 13/24] iommu/mediatek: Add infra iommu support Yong Wu
2021-06-30  2:34 ` [PATCH 14/24] iommu/mediatek: Add PCIe support Yong Wu
2021-06-30  2:34 ` [PATCH 15/24] iommu/mediatek: Add mt8195 support Yong Wu
2021-06-30  2:34 ` [PATCH 16/24] iommu/mediatek: Only adjust code about register base Yong Wu
2021-06-30  2:34 ` [PATCH 17/24] iommu/mediatek: Just move code position in hw_init Yong Wu
2021-06-30  2:34 ` [PATCH 18/24] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2021-06-30  2:34 ` [PATCH 19/24] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2021-06-30  2:35 ` [PATCH 20/24] iommu/mediatek: Add bank_nr and bank_enable Yong Wu
2021-06-30  2:35 ` [PATCH 21/24] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2021-06-30  2:35 ` [PATCH 22/24] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2021-06-30  2:35 ` [PATCH 23/24] iommu/mediatek: Add multi bank support Yong Wu
2021-06-30  2:35 ` [PATCH 24/24] iommu/mediatek: mt8195: Enable multi-bank for infra iommu Yong Wu

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