From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Joshua Yeong <joshua.yeong@starfivetech.com>
Cc: <pgaj@cadence.com>, <alexandre.belloni@bootlin.com>,
<linux-i3c@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/1] i3c: master: cdns: Fix reading status register
Date: Tue, 12 Sep 2023 12:57:04 +0200 [thread overview]
Message-ID: <20230912125704.5fb1a102@xps-13> (raw)
In-Reply-To: <20230911081623.21963-2-joshua.yeong@starfivetech.com>
Hi Joshua,
joshua.yeong@starfivetech.com wrote on Mon, 11 Sep 2023 16:16:24 +0800:
> IBIR_DEPTH and CMDR_DEPTH should read from status0 instead of status1
be
Missing '.' at the end.
Missing Fixes: tag as well as Cc: stable.
>
> Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
> ---
> drivers/i3c/master/i3c-master-cdns.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c
> index 49551db71bc9..8f1fda3c7ac5 100644
> --- a/drivers/i3c/master/i3c-master-cdns.c
> +++ b/drivers/i3c/master/i3c-master-cdns.c
> @@ -191,7 +191,7 @@
> #define SLV_STATUS1_HJ_DIS BIT(18)
> #define SLV_STATUS1_MR_DIS BIT(17)
> #define SLV_STATUS1_PROT_ERR BIT(16)
> -#define SLV_STATUS1_DA(x) (((s) & GENMASK(15, 9)) >> 9)
> +#define SLV_STATUS1_DA(s) (((s) & GENMASK(15, 9)) >> 9)
> #define SLV_STATUS1_HAS_DA BIT(8)
> #define SLV_STATUS1_DDR_RX_FULL BIT(7)
> #define SLV_STATUS1_DDR_TX_FULL BIT(6)
> @@ -1623,13 +1623,13 @@ static int cdns_i3c_master_probe(struct platform_device *pdev)
> /* Device ID0 is reserved to describe this master. */
> master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
> master->free_rr_slots = GENMASK(master->maxdevs, 1);
> + master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
> + master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
>
> val = readl(master->regs + CONF_STATUS1);
> master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
> master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
> master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
> - master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
> - master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
>
> spin_lock_init(&master->ibi.lock);
> master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);
Thanks,
Miquèl
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prev parent reply other threads:[~2023-09-12 10:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-11 8:16 [PATCH 0/1] Cadence I3C Status Register Bit Mask Error Joshua Yeong
2023-09-11 8:16 ` [PATCH 1/1] i3c: master: cdns: Fix reading status register Joshua Yeong
2023-09-12 10:57 ` Miquel Raynal [this message]
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