From: Mark Brown <broonie@kernel.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Patrick Rudolph <patrick.rudolph@9elements.com>,
naresh.solanki@9elements.com, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] pinctrl: cy8c95x0: Cache muxed registers
Date: Tue, 14 May 2024 10:30:38 +0100 [thread overview]
Message-ID: <2008e2e7-59f6-437c-a3c6-1fb9e31bf635@sirena.org.uk> (raw)
In-Reply-To: <CAHp75VdDMOLuRhDNQ=dzoE6Yyah+k-pGm8vY8B2DmFiyPBuftw@mail.gmail.com>
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On Tue, May 14, 2024 at 12:23:19PM +0300, Andy Shevchenko wrote:
> On Tue, May 14, 2024 at 12:02 PM Mark Brown <broonie@kernel.org> wrote:
> > If there's paging of registers then regmap supports this with the ranges
> > feature, you can tell regmap where the window is in the physical
> > register map and which register to use to switch pages and have regmap
> > export the underlying registers as a linear range of virtual registers.
> In this chip there are two ranges that are dependent on a selector,
> one is for port selection (which the original change is about) and
> another is for PWM (IIRC). Note that they are orthogonal to each
> other, meaning they have their own selector registers.
That's fine, you can have as many ranges as you like.
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next prev parent reply other threads:[~2024-05-14 9:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 12:53 [PATCH] pinctrl: cy8c95x0: Cache muxed registers Patrick Rudolph
2023-12-20 12:04 ` Linus Walleij
2024-05-14 5:27 ` Andy Shevchenko
2024-05-14 7:49 ` Linus Walleij
2024-05-14 8:39 ` Patrick Rudolph
2024-05-14 8:51 ` Linus Walleij
2024-05-14 8:55 ` Andy Shevchenko
2024-05-14 8:57 ` Andy Shevchenko
2024-05-14 9:02 ` Mark Brown
2024-05-14 9:23 ` Andy Shevchenko
2024-05-14 9:30 ` Mark Brown [this message]
2024-05-14 8:55 ` Mark Brown
2024-05-16 17:03 ` Patrick Rudolph
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