From: Michal Simek <michal.simek@amd.com>
To: Xu Yilun <yilun.xu@linux.intel.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: linux-kernel@vger.kernel.org, monstr@monstr.eu,
michal.simek@xilinx.com, git@xilinx.com,
Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Moritz Fischer <mdf@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Tom Rix <trix@redhat.com>, Wu Hao <hao.wu@intel.com>,
Xu Yilun <yilun.xu@intel.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
kishore Manne <nava.kishore.manne@amd.com>,
"open list:FPGA MANAGER FRAMEWORK" <linux-fpga@vger.kernel.org>
Subject: Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml
Date: Tue, 9 Jan 2024 14:31:21 +0100 [thread overview]
Message-ID: <c50564da-87c9-47dc-a546-779a6a82928b@amd.com> (raw)
In-Reply-To: <ZZ0eVZGcYJ0sFxh2@yilunxu-OptiPlex-7050>
On 1/9/24 11:22, Xu Yilun wrote:
> On Tue, Jan 09, 2024 at 09:16:33AM +0100, Krzysztof Kozlowski wrote:
>> On 09/01/2024 09:15, Krzysztof Kozlowski wrote:
>>>>>>>>> +properties:
>>>>>>>>> + $nodename:
>>>>>>>>> + pattern: "^fpga-bridge(@.*)?$"
>>>>>>>>
>>>>>>>> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
>>>>>>>> than one bridge on given system?
>>>>>>>
>>>>>>> Yilun: Any comment on this?
>>>>>>
>>>>>> We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
>>>>>> to identify them. So the expression is OK to me.
>>>>>
>>>>> So you claim unit address thus reg with some sort of bus address is a
>>>>> requirement? Then "?" is not correct in that pattern.
>>>>
>>>> I expect it is about that people are using fpga-bridge@0 but bridge is not on
>>>> the bus. Yilun said that reg property in altr,socfpga-fpga2sdram-bridge.yaml is
>>>> optional which means no reg property no @XXX in node name.
>>>> That's why I think that expression is correct. If there are more bridges without
>>>> reg property then I expect we need to get more examples to align expression.
>>>
>>> If we allow node name without unit address, thus not being part of any
>
> This is valid usecase.
>
>>> bus, then the only question is whether it is possible to have system
>>> with more than two FPGA bridges. If the answer is "yes", which I think
>
> The answer is yes.
>
>>> is the case, then the pattern should already allow it:
>>>
>>> (@[0-9a-f]+|-[0-9]+)?
>>
>> Or better go with what I used recently for narrowed choices:
>>
>> (@.*|-([0-9]|[1-9][0-9]+))?
>
> It is good to me.
>
> I actually didn't know much about DTS & its Schema, thanks for all your
> input.
Ok. Will send v3 with it.
Thanks,
Michal
next prev parent reply other threads:[~2024-01-09 13:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-05 16:04 [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml Michal Simek
2024-01-05 16:04 ` [PATCH 2/2] dt-bindings: fpga: altera: Convert bridge bindings " Michal Simek
2024-01-08 7:46 ` Xu Yilun
2024-01-08 8:12 ` Michal Simek
2024-01-09 4:04 ` Xu Yilun
2024-01-08 9:12 ` Krzysztof Kozlowski
2024-01-08 7:47 ` [PATCH 1/2] dt-bindings: fpga: Convert bridge binding " Xu Yilun
2024-01-08 9:09 ` Krzysztof Kozlowski
2024-01-08 9:16 ` Michal Simek
2024-01-09 3:53 ` Xu Yilun
2024-01-09 8:00 ` Krzysztof Kozlowski
2024-01-09 8:06 ` Michal Simek
2024-01-09 8:15 ` Krzysztof Kozlowski
2024-01-09 8:16 ` Krzysztof Kozlowski
2024-01-09 10:22 ` Xu Yilun
2024-01-09 13:31 ` Michal Simek [this message]
2024-01-09 8:20 ` Michal Simek
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