From: Xu Yilun <yilun.xu@intel.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: Wu Hao <hao.wu@intel.com>, Tom Rix <trix@redhat.com>,
Moritz Fischer <mdf@kernel.org>,
linux-fpga@vger.kernel.org, Lee Jones <lee@kernel.org>,
Jean Delvare <jdelvare@suse.com>,
Guenter Roeck <linux@roeck-us.net>,
linux-hwmon@vger.kernel.org,
Russ Weight <russell.h.weight@intel.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/4] mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers
Date: Fri, 14 Apr 2023 11:45:26 +0000 [thread overview]
Message-ID: <ZDk81v7DuSVh6228@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <fb95c8da-c828-12b8-aae-56bd867cff41@linux.intel.com>
On 2023-04-11 at 14:54:58 +0300, Ilpo Järvinen wrote:
> On Fri, 7 Apr 2023, Xu Yilun wrote:
>
> > On 2023-04-05 at 11:01:52 +0300, Ilpo Järvinen wrote:
> > > On some MAX 10 cards, the BMC firmware is not available to service
> > > handshake registers during secure update erase and write phases at
> > > normal speeds. This problem affects at least hwmon driver. When the MAX
> > > 10 hwmon driver tries to read the sensor values during a secure update,
> > > the reads are slowed down (e.g., reading all D5005 sensors takes ~24s
> > > which is magnitudes worse than the normal <0.02s).
> > >
> > > Manage access to the handshake registers using a rw semaphore and a FW
> > > state variable to prevent accesses during those secure update phases
> > > and return -EBUSY instead.
> > >
> > > Co-developed-by: Russ Weight <russell.h.weight@intel.com>
> > > Signed-off-by: Russ Weight <russell.h.weight@intel.com>
> > > Co-developed-by: Xu Yilun <yilun.xu@intel.com>
> > > Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> > > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> > > ---
> > > drivers/fpga/intel-m10-bmc-sec-update.c | 17 +++++--
> > > drivers/mfd/intel-m10-bmc-core.c | 63 ++++++++++++++++++++++++-
> > > drivers/mfd/intel-m10-bmc-pmci.c | 4 ++
> > > drivers/mfd/intel-m10-bmc-spi.c | 14 ++++++
> > > include/linux/mfd/intel-m10-bmc.h | 27 +++++++++++
> > > 5 files changed, 120 insertions(+), 5 deletions(-)
> > >
> >
> > [...]
> >
> > >
> > > +void m10bmc_fw_state_set(struct intel_m10bmc *m10bmc, enum m10bmc_fw_state new_state)
> > > +{
> > > + down_write(&m10bmc->bmcfw_lock);
> > > + m10bmc->bmcfw_state = new_state;
> > > + up_write(&m10bmc->bmcfw_lock);
> >
> > Could we also skip this if no handshake is possible like for PMCI?
>
> Did you mean guarding it with !m10bmc->info->handshake_sys_reg_nranges ?
Yes. My concern is, the handshake_sys_reg_nranges is the constant value
for a device, so if the device doesn't have handshake registers, we
could save the locking costs.
Thanks,
Yilun
> If yes, it's doable (+ I'd add comment mentioning it since it's slightly
> trappy to not always have that state updated).
>
>
> --
> i.
prev parent reply other threads:[~2023-04-14 3:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-05 8:01 [PATCH 0/4] Manage register access to control delay during sec update Ilpo Järvinen
2023-04-05 8:01 ` [PATCH 1/4] mfd: intel-m10-bmc: Move core symbols to own namespace Ilpo Järvinen
2023-04-05 18:38 ` Russ Weight
2023-04-07 6:26 ` Xu Yilun
2023-04-11 11:40 ` Ilpo Järvinen
2023-04-05 8:01 ` [PATCH 2/4] mfd: intel-m10-bmc: Create m10bmc_sys_update_bits() Ilpo Järvinen
2023-04-05 8:01 ` [PATCH 3/4] mfd: intel-m10-bmc: Move m10bmc_sys_read() away from header Ilpo Järvinen
2023-04-05 12:43 ` Guenter Roeck
2023-04-05 18:40 ` Russ Weight
2023-04-05 8:01 ` [PATCH 4/4] mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers Ilpo Järvinen
2023-04-07 6:10 ` Xu Yilun
2023-04-11 11:45 ` Ilpo Järvinen
2023-04-07 6:18 ` Xu Yilun
2023-04-11 11:54 ` Ilpo Järvinen
2023-04-14 11:45 ` Xu Yilun [this message]
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