From: Charles Perry <charles.perry@savoirfairelinux.com>
To: Xu Yilun <yilun.xu@linux.intel.com>, Kris Chaplin <kris.chaplin@amd.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
mdf <mdf@kernel.org>, Michal Simek <michal.simek@amd.com>,
hao wu <hao.wu@intel.com>, yilun xu <yilun.xu@intel.com>,
trix <trix@redhat.com>,
krzysztof kozlowski+dt <krzysztof.kozlowski+dt@linaro.org>,
Brian CODY <bcody@markem-imaje.com>,
Allen VANDIVER <avandiver@markem-imaje.com>,
linux-fpga <linux-fpga@vger.kernel.org>,
devicetree <devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema
Date: Tue, 13 Feb 2024 16:54:44 -0500 (EST) [thread overview]
Message-ID: <2031953666.970772.1707861284199.JavaMail.zimbra@savoirfairelinux.com> (raw)
In-Reply-To: <Zb9LDQP3xzrv6LWr@yilunxu-OptiPlex-7050>
On Feb 4, 2024, at 3:30 AM, Xu Yilun yilun.xu@linux.intel.com wrote:
> On Wed, Jan 31, 2024 at 11:03:25AM +0000, Kris Chaplin wrote:
>> Hello Krzysztof,
>>
>> On 30/01/2024 16:09, Krzysztof Kozlowski wrote:
>>
>> > > +
>> > > +description: |
>> > > + Xilinx 7 Series FPGAs support a method of loading the bitstream over a
>> > > + parallel port named the slave SelectMAP interface in the documentation. Only
>> > > + the x8 mode is supported where data is loaded at one byte per rising edge of
>> > > + the clock, with the MSB of each byte presented to the D0 pin.
>> > > +
>> > > + Datasheets:
>> > > +
>> > > https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
>> >
>> > I am surprised that AMD/Xilinx still did not update the document to
>> > modern naming (slave->secondary).
>>
>> Thank you for bringing this up.
>>
>> We are moving away from using non-inclusive technical terminology and are
>> removing non-inclusive language from our products and related collateral.
>> You will for some time find examples of non-inclusive language, especially
>> in our older products as we work to make these changes and align with
>> industry standards. For new IP we're ensuring that we switch and stick to
>> inclusive terminology, as you may have seen with my recent w1 driver
>> submission.
>>
>> SelectMAP is a decades-old interface and as such it is unlikely that we will
>> update this in all documentation dating back this time. I shall however
>> look to understand what is planned here for active documentation and new
>> driver submissions.
>
> Yes, I need review from AMD/Xilinx side. Especially the HW parts, and
> some namings of variables, e.g. if xilinx-core is proper for what products
> it supports, and won't be an issue in future.
>
> Thanks,
> Yilun
>
>>
>> regards
>> Kris
Hello,
I chose the "-core" suffix as it seems widely used for core logic of device
drivers for chips that comes in an i2c and spi flavour. It seems like "-common"
is also widespread, let me know if you prefer that suffix.
As for the HW parts, here's the compatibles used in the v3 patchset for
convenience:
- xlnx,fpga-xc7s-selectmap
- xlnx,fpga-xc7a-selectmap
- xlnx,fpga-xc7k-selectmap
- xlnx,fpga-xc7v-selectmap
We're trying to be a bit more specific than the spi interface which uses
"xlnx,fpga-slave-serial"
Regards,
Charles
next prev parent reply other threads:[~2024-02-13 21:54 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-29 22:56 [PATCH 1/3] fpga: xilinx-spi: extract a common driver core Charles Perry
2024-01-29 22:56 ` [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Charles Perry
2024-01-30 0:21 ` Rob Herring
2024-01-30 7:52 ` Krzysztof Kozlowski
2024-01-30 7:53 ` Krzysztof Kozlowski
2024-01-30 15:45 ` Charles Perry
2024-01-30 16:05 ` Krzysztof Kozlowski
2024-01-30 17:05 ` Charles Perry
2024-01-30 17:58 ` Krzysztof Kozlowski
2024-01-30 23:32 ` Charles Perry
2024-01-30 16:09 ` Krzysztof Kozlowski
2024-01-31 11:03 ` Kris Chaplin
2024-02-04 8:30 ` Xu Yilun
2024-02-13 21:54 ` Charles Perry [this message]
2024-01-29 22:56 ` [PATCH 3/3] fpga: xilinx-selectmap: add new driver Charles Perry
2024-01-30 7:56 ` Krzysztof Kozlowski
2024-01-31 23:05 ` [PATCH 0/3] " Charles Perry
2024-01-31 23:05 ` [PATCH 1/3] fpga: xilinx-spi: extract a common driver core Charles Perry
2024-02-04 8:22 ` Xu Yilun
2024-02-06 15:39 ` Charles Perry
2024-01-31 23:05 ` [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Charles Perry
2024-02-01 8:07 ` Krzysztof Kozlowski
2024-02-01 18:24 ` Charles Perry
2024-02-02 10:49 ` Krzysztof Kozlowski
2024-02-02 19:52 ` Charles Perry
2024-01-31 23:05 ` [PATCH 3/3] fpga: xilinx-selectmap: add new driver Charles Perry
2024-02-04 8:10 ` Xu Yilun
2024-02-06 15:48 ` Charles Perry
2024-02-02 20:16 ` [PATCH 0/3] " Rob Herring
2024-02-02 20:53 ` Charles Perry
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