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From: Dan Williams <dan.j.williams@intel.com>
To: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>
Cc: <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
	<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
	<Jonathan.Cameron@huawei.com>, <dave@stgolabs.net>
Subject: Re: [PATCH v5 4/4] cxl: Add checks to access_coordinate calculation to fail missing data
Date: Mon, 1 Apr 2024 12:37:51 -0700	[thread overview]
Message-ID: <660b0d0f5c83a_15786294fd@dwillia2-mobl3.amr.corp.intel.com.notmuch> (raw)
In-Reply-To: <20240325230234.1847525-5-dave.jiang@intel.com>

Dave Jiang wrote:
> Jonathan noted that when the coordinates for host bridge and switches
> can be 0s if no actual data are retrieved and the calculation continues.
> The resulting number would be inaccurate. Add checks to ensure that the
> calculation would complete only if the numbers are valid.
> 
> While not seen in the wild, issue may show up with a BIOS that reported
> CXL root ports via Generic Ports (via a PCI handle in the SRAT entry).
> 
> Fixes: 14a6960b3e92 ("cxl: Add helper function that calculate performance data for downstream ports")
> Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v5:
> - Adjust for multiple access classes.
> ---
>  drivers/cxl/core/port.c | 38 +++++++++++++++++++++++++++-----------
>  1 file changed, 27 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index e388f50675f8..ca5bc9ed6d2f 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -2141,6 +2141,18 @@ static void add_latency(struct access_coordinate *c, long latency)
>  	}
>  }
>  
> +static bool coordinates_valid(struct access_coordinate *c)
> +{
> +	for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
> +		if (c[i].read_bandwidth && c[i].write_bandwidth &&
> +		    c[i].read_latency && c[i].write_latency)
> +			continue;
> +		return false;

With the observation that a coordinate tracks nanoseconds while the CDAT
reports picoseconds I wonder what this check does for sub-nanosecond
latency values. Does that need a min_not_zero(1, latency) somewhere...
and if that is in place does it mean latency can never be zero?

      reply	other threads:[~2024-04-01 19:37 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-25 23:00 [PATCH v5 0/4] cxl: access_coordinate validity fixes for 6.9 Dave Jiang
2024-03-25 23:00 ` [PATCH v5 1/4] cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates() Dave Jiang
2024-03-29  1:26   ` Dan Williams
2024-03-25 23:00 ` [PATCH v5 2/4] cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord Dave Jiang
2024-03-29  1:28   ` Dan Williams
2024-03-25 23:00 ` [PATCH v5 3/4] cxl: Fix incorrect region perf data calculation Dave Jiang
2024-04-01 19:33   ` Dan Williams
2024-03-25 23:00 ` [PATCH v5 4/4] cxl: Add checks to access_coordinate calculation to fail missing data Dave Jiang
2024-04-01 19:37   ` Dan Williams [this message]

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