From: Yao Xingtao <yaoxt.fnst@fujitsu.com>
To: dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, ira.weiny@intel.com,
dan.j.williams@intel.com, jim.harris@samsung.com
Cc: linux-cxl@vger.kernel.org, Yao Xingtao <yaoxt.fnst@fujitsu.com>
Subject: [PATCH v4 2/2] cxl/region: check interleave capability
Date: Mon, 22 Apr 2024 05:13:50 -0400 [thread overview]
Message-ID: <20240422091350.4701-3-yaoxt.fnst@fujitsu.com> (raw)
In-Reply-To: <20240422091350.4701-1-yaoxt.fnst@fujitsu.com>
Since interleave capability is not verified, a target can successfully
attach to a region even if it lacks support for the specified interleave
ways or granularity.
When attempting to access memory, unexpected behavior occurs due to the
incorrect conversion of HPA to a faulty DPA, leading to a segmentation
fault, as observed when executing the command:
$ numactl -m 2 ls
According to the CXL specification (section 8.2.4.20 CXL HDM Decoder
Capability Structure), bits 11 and 12 within the 'CXL HDM Decoder
Capability Register' indicate the capability to establish interleaving
in 3, 6, 12, and 16 ways. If these bits are not set, the target cannot
be attached to a region utilizing such interleave ways.
Additionally, bits 8 and 9 in the same register represent the capability
of the bits used for interleaving in the address, commonly referred to as
the interleave mask.
Regarding 'Decoder Protection':
If IW is less than 8 (for interleave ways of 1, 2, 4, 8, 16), the
interleave bits start at bit position IG + 8 and end at IG + IW + 8 - 1.
If the IW is greater than or equal to 8 (for interleave ways of 3, 6, 12),
the interleave bits start at bit position IG + 8 and end at IG + IW - 1.
If the interleave mask is insufficient to cover the required interleave
bits, the target cannot be attached to the region.
The above check does not apply to the host-bridges with single port and
switches with single dport, because there does not have a instance of
CXL HDM Decoder Capability Structure for them.
Fixes: 384e624bb211 ("cxl/region: Attach endpoint decoders")
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
---
drivers/cxl/core/hdm.c | 5 +++
drivers/cxl/core/region.c | 70 +++++++++++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 2 ++
drivers/cxl/cxlmem.h | 1 +
4 files changed, 78 insertions(+)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 27fb4f9d489e..b201be4b8d76 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -80,6 +80,11 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
cxlhdm->interleave_mask |= GENMASK(11, 8);
if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap))
cxlhdm->interleave_mask |= GENMASK(14, 12);
+ cxlhdm->iw_cap_mask = BIT(1) | BIT(2) | BIT(4) | BIT(8);
+ if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap))
+ cxlhdm->iw_cap_mask |= BIT(3) | BIT(6) | BIT(12);
+ if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap))
+ cxlhdm->iw_cap_mask |= BIT(16);
}
static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 5c186e0a39b9..5c09652136c9 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -1210,6 +1210,60 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled,
return 0;
}
+static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig)
+{
+ struct cxl_port *port = to_cxl_port(cxld->dev.parent);
+ struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
+ struct cxl_switch_decoder *cxlsd;
+ unsigned int interleave_mask;
+ u8 eiw;
+ u16 eig;
+ int rc, high_pos, low_pos;
+
+ if (is_switch_decoder(&cxld->dev)) {
+ cxlsd = to_cxl_switch_decoder(&cxld->dev);
+ if (cxlsd->passthrough)
+ return 0;
+ }
+
+ rc = ways_to_eiw(iw, &eiw);
+ if (rc)
+ return rc;
+
+ if (!(cxlhdm->iw_cap_mask & BIT(iw)))
+ return -EOPNOTSUPP;
+
+ rc = granularity_to_eig(ig, &eig);
+ if (rc)
+ return rc;
+
+ /*
+ * Per CXL specification (8.2.3.20.13 Decoder Protection in r3.1)
+ * if IW < 8, the interleave bits start at bit position IG + 8, and
+ * end at IG + IW + 8 - 1.
+ * if IW >= 8, the interleave bits start at bit position IG + 8, and
+ * end at IG + IW - 1.
+ */
+ if (eiw >= 8)
+ high_pos = eiw + eig - 1;
+ else
+ high_pos = eiw + eig + 7;
+ low_pos = eig + 8;
+ /*
+ * when the IW is 0 or 8 (interlave way is 1 or 3), the low_pos is
+ * larger than high_pos, since the target is in the target list of a
+ * passthrough decoder, the following check is ignored.
+ */
+ if (low_pos > high_pos)
+ return 0;
+
+ interleave_mask = GENMASK(high_pos, low_pos);
+ if (interleave_mask & ~cxlhdm->interleave_mask)
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
static int cxl_port_setup_targets(struct cxl_port *port,
struct cxl_region *cxlr,
struct cxl_endpoint_decoder *cxled)
@@ -1360,6 +1414,14 @@ static int cxl_port_setup_targets(struct cxl_port *port,
return -ENXIO;
}
} else {
+ rc = check_interleave_cap(cxld, iw, ig);
+ if (rc) {
+ dev_dbg(&cxlr->dev,
+ "%s:%s iw: %d ig: %d is not supported\n",
+ dev_name(port->uport_dev),
+ dev_name(&port->dev), iw, ig);
+ return rc;
+ }
cxld->interleave_ways = iw;
cxld->interleave_granularity = ig;
cxld->hpa_range = (struct range) {
@@ -1796,6 +1858,14 @@ static int cxl_region_attach(struct cxl_region *cxlr,
struct cxl_dport *dport;
int rc = -ENXIO;
+ rc = check_interleave_cap(&cxled->cxld, p->interleave_ways,
+ p->interleave_granularity);
+ if (rc) {
+ dev_dbg(&cxlr->dev, "%s iw: %d ig: %d is not supported\n",
+ dev_name(&cxled->cxld.dev), p->interleave_ways,
+ p->interleave_granularity);
+ return rc;
+ }
if (cxled->mode != cxlr->mode) {
dev_dbg(&cxlr->dev, "%s region mode: %d mismatch: %d\n",
dev_name(&cxled->cxld.dev), cxlr->mode, cxled->mode);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 6f562baa164f..b7afb936c854 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -45,6 +45,8 @@
#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
#define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
#define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
+#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11)
+#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12)
#define CXL_HDM_DECODER_CTRL_OFFSET 0x4
#define CXL_HDM_DECODER_ENABLE BIT(1)
#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 36cee9c30ceb..a044234f5993 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -853,6 +853,7 @@ struct cxl_hdm {
unsigned int decoder_count;
unsigned int target_count;
unsigned int interleave_mask;
+ unsigned int iw_cap_mask;
struct cxl_port *port;
};
--
2.37.3
next prev parent reply other threads:[~2024-04-22 9:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-22 9:13 [PATCH v4 0/2] cxl/region: add interleave capability check Yao Xingtao
2024-04-22 9:13 ` [PATCH v4 1/2] cxl/core: add passthrough flag to struct cxl_switch_decoder Yao Xingtao
2024-04-22 11:12 ` Jonathan Cameron
2024-04-22 23:56 ` Xingtao Yao (Fujitsu)
2024-04-23 0:37 ` Dan Williams
2024-04-22 9:13 ` Yao Xingtao [this message]
2024-04-22 11:17 ` [PATCH v4 2/2] cxl/region: check interleave capability Jonathan Cameron
2024-04-23 0:02 ` Xingtao Yao (Fujitsu)
2024-04-23 0:59 ` Dan Williams
2024-04-23 2:47 ` Xingtao Yao (Fujitsu)
2024-05-12 23:43 ` Xingtao Yao (Fujitsu)
2024-05-23 9:05 ` Xingtao Yao (Fujitsu)
2024-05-23 18:47 ` Dan Williams
2024-05-24 9:15 ` Xingtao Yao (Fujitsu)
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