From: Yuquan Wang <wangyuquan1236@phytium.com.cn>
To: ira.weiny@intel.com, jonathan.cameron@huawei.com,
dan.j.williams@intel.com
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
qemu-devel@nongnu.org, chenbaozi@phytium.com.cn,
Yuquan Wang <wangyuquan1236@phytium.com.cn>
Subject: [PATCH v2 0/1] cxl/mem: Fix for the index of Clear Event Record Handle
Date: Mon, 18 Mar 2024 10:29:27 +0800 [thread overview]
Message-ID: <20240318022928.509130-1-wangyuquan1236@phytium.com.cn> (raw)
This is a simple fix for the index of 'Clear Event Record' Handle. The
print content of dev_dbg from Clear Event Records mailbox command would
report the handle of the next record to clear not the current one.
The problem was found when I was doing the debug of CXL Event Error on
Qemu. I injected an individual event through QMP
'cxl-inject-general-media-event':
{ "execute": "cxl-inject-general-media-event",
"arguments": {
"path": "/machine/peripheral/cxl-mem0",
"log": "informational",
"flags": 1,
"dpa": 1000,
"descriptor": 3,
"type": 3,
"transaction-type": 192,
"channel": 3,
"device": 5,
"component-id": "iras mem"
}}
Then the kernel printed:
[ 1639.106181] cxl_pci 0000:0d:00.0: Event log '0': Clearing 0
However, the line 36 in 'hw/cxl/cxl-events.c': log->next_handle = 1;
It will set the actual handle value of injected event to '1'.
With this fix, the kernel will print:
[ 122.456750] cxl_pci 0000:0d:00.0: Event log '0': Clearing 1
which is in line with the simulated value in Qemu.
Yuquan Wang (1):
cxl/mem: Fix for the index of Clear Event Record Handle
drivers/cxl/core/mbox.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.34.1
next reply other threads:[~2024-03-18 2:29 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-18 2:29 Yuquan Wang [this message]
2024-03-18 2:29 ` [PATCH v2 1/1] cxl/mem: Fix for the index of Clear Event Record Handle Yuquan Wang
2024-03-18 10:57 ` Jonathan Cameron
2024-03-19 0:38 ` Dan Williams
2024-03-19 18:31 ` Dave Jiang
2024-03-18 16:51 ` fan
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