From: Dmitry Rokosov <ddrokosov@salutedevices.com>
To: <neil.armstrong@linaro.org>, <jbrunet@baylibre.com>,
<mturquette@baylibre.com>, <sboyd@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<khilman@baylibre.com>, <martin.blumenstingl@googlemail.com>
Cc: <jian.hu@amlogic.com>, <kernel@sberdevices.ru>,
<rockosov@gmail.com>, <linux-amlogic@lists.infradead.org>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Dmitry Rokosov <ddrokosov@salutedevices.com>
Subject: [PATCH v3 1/7] clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL
Date: Wed, 15 May 2024 21:47:24 +0300 [thread overview]
Message-ID: <20240515185103.20256-2-ddrokosov@salutedevices.com> (raw)
In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com>
When dealing with certain PLLs, it is necessary to avoid modifying them
if they have already been initialized by lower levels. For instance, in
the A1 SoC Family, the sys_pll is enabled as the parent for the cpuclk,
and it cannot be disabled during the initialization sequence. Therefore,
initialization phase must be skipped.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
---
drivers/clk/meson/clk-pll.c | 40 ++++++++++++++++++++++---------------
drivers/clk/meson/clk-pll.h | 1 +
2 files changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 78d17b2415af..e1132a110aab 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -289,11 +289,35 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw)
return -ETIMEDOUT;
}
+static int meson_clk_pll_is_enabled(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+
+ if (MESON_PARM_APPLICABLE(&pll->rst) &&
+ meson_parm_read(clk->map, &pll->rst))
+ return 0;
+
+ if (!meson_parm_read(clk->map, &pll->en) ||
+ !meson_parm_read(clk->map, &pll->l))
+ return 0;
+
+ return 1;
+}
+
static int meson_clk_pll_init(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+ /*
+ * Keep the clock running, which was already initialized and enabled
+ * from the bootloader stage, to avoid any glitches.
+ */
+ if ((pll->flags & CLK_MESON_PLL_NOINIT_ENABLED) &&
+ meson_clk_pll_is_enabled(hw))
+ return 0;
+
if (pll->init_count) {
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
@@ -308,22 +332,6 @@ static int meson_clk_pll_init(struct clk_hw *hw)
return 0;
}
-static int meson_clk_pll_is_enabled(struct clk_hw *hw)
-{
- struct clk_regmap *clk = to_clk_regmap(hw);
- struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
-
- if (MESON_PARM_APPLICABLE(&pll->rst) &&
- meson_parm_read(clk->map, &pll->rst))
- return 0;
-
- if (!meson_parm_read(clk->map, &pll->en) ||
- !meson_parm_read(clk->map, &pll->l))
- return 0;
-
- return 1;
-}
-
static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
{
int retries = 10;
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index a2228c0fdce5..7b6b87274073 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -28,6 +28,7 @@ struct pll_mult_range {
}
#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
+#define CLK_MESON_PLL_NOINIT_ENABLED BIT(1)
struct meson_clk_pll_data {
struct parm en;
--
2.43.0
next prev parent reply other threads:[~2024-05-15 18:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 18:47 [PATCH v3 0/7] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver Dmitry Rokosov
2024-05-15 18:47 ` Dmitry Rokosov [this message]
2024-05-15 18:47 ` [PATCH v3 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Dmitry Rokosov
2024-05-20 19:02 ` Rob Herring (Arm)
2024-05-15 18:47 ` [PATCH v3 3/7] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Dmitry Rokosov
2024-05-15 18:47 ` [PATCH v3 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll input Dmitry Rokosov
2024-05-15 19:00 ` Dmitry Rokosov
2024-05-20 19:18 ` Rob Herring (Arm)
2024-05-15 18:47 ` [PATCH v3 5/7] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input Dmitry Rokosov
2024-05-15 18:47 ` [PATCH v3 6/7] dt-bindings: clock: meson: add A1 CPU clock controller bindings Dmitry Rokosov
2024-05-15 18:47 ` [PATCH v3 7/7] clk: meson: a1: add Amlogic A1 CPU clock controller driver Dmitry Rokosov
2024-05-28 17:41 ` [PATCH v3 0/7] clk: meson: introduce Amlogic A1 SoC Family " Dmitry Rokosov
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