From: Dmitry Rokosov <ddrokosov@salutedevices.com>
To: <neil.armstrong@linaro.org>, <jbrunet@baylibre.com>,
<mturquette@baylibre.com>, <sboyd@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<khilman@baylibre.com>, <martin.blumenstingl@googlemail.com>
Cc: <jian.hu@amlogic.com>, <kernel@sberdevices.ru>,
<rockosov@gmail.com>, <linux-amlogic@lists.infradead.org>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Dmitry Rokosov <ddrokosov@salutedevices.com>
Subject: [PATCH v2 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
Date: Fri, 10 May 2024 12:08:54 +0300 [thread overview]
Message-ID: <20240510090933.19464-3-ddrokosov@salutedevices.com> (raw)
In-Reply-To: <20240510090933.19464-1-ddrokosov@salutedevices.com>
The 'syspll' PLL is a general-purpose PLL designed specifically for the
CPU clock. It is capable of producing output frequencies within the
range of 768MHz to 1536MHz.
The clock source sys_pll_div16, being one of the GEN clock parents,
plays a crucial role and cannot be tagged as "optional". Unfortunately,
it was not implemented earlier due to the cpu clock ctrl driver's
pending status on the TODO list.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
---
.../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +++++--
include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 ++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
index a59b188a8bf5..fbba57031278 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
@@ -26,11 +26,13 @@ properties:
items:
- description: input fixpll_in
- description: input hifipll_in
+ - description: input syspll_in
clock-names:
items:
- const: fixpll_in
- const: hifipll_in
+ - const: syspll_in
required:
- compatible
@@ -53,7 +55,8 @@ examples:
reg = <0 0x7c80 0 0x18c>;
#clock-cells = <1>;
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
- <&clkc_periphs CLKID_HIFIPLL_IN>;
- clock-names = "fixpll_in", "hifipll_in";
+ <&clkc_periphs CLKID_HIFIPLL_IN>,
+ <&clkc_periphs CLKID_SYSPLL_IN>;
+ clock-names = "fixpll_in", "hifipll_in", "syspll_in";
};
};
diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
index 2b660c0f2c9f..a702d610589c 100644
--- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
+++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
@@ -21,5 +21,7 @@
#define CLKID_FCLK_DIV5 8
#define CLKID_FCLK_DIV7 9
#define CLKID_HIFI_PLL 10
+#define CLKID_SYS_PLL 11
+#define CLKID_SYS_PLL_DIV16 12
#endif /* __A1_PLL_CLKC_H */
--
2.43.0
next prev parent reply other threads:[~2024-05-10 9:09 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 9:08 [PATCH v2 0/7] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 1/7] clk: meson: introduce 'INIT_ONCE' flag to eliminate init for enabled PLL Dmitry Rokosov
2024-05-13 12:44 ` Jerome Brunet
2024-05-13 21:47 ` Dmitry Rokosov
2024-05-15 13:12 ` Jerome Brunet
2024-05-10 9:08 ` Dmitry Rokosov [this message]
2024-05-11 13:08 ` [PATCH v2 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Conor Dooley
2024-05-13 9:18 ` Dmitry Rokosov
2024-05-13 15:48 ` Conor Dooley
2024-05-13 18:30 ` Dmitry Rokosov
2024-05-15 13:15 ` Jerome Brunet
2024-05-13 12:04 ` Jerome Brunet
2024-05-13 15:42 ` Conor Dooley
2024-05-10 9:08 ` [PATCH v2 3/7] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Dmitry Rokosov
2024-05-13 12:48 ` Jerome Brunet
2024-05-13 21:25 ` Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input Dmitry Rokosov
2024-05-11 13:03 ` Conor Dooley
2024-05-13 12:02 ` Jerome Brunet
2024-05-10 9:08 ` [PATCH v2 5/7] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 6/7] dt-bindings: clock: meson: add A1 CPU clock controller bindings Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 7/7] clk: meson: a1: add Amlogic A1 CPU clock controller driver Dmitry Rokosov
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