From: Heiko Stuebner <heiko@sntech.de>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>,
linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de,
patchwork-lst@pengutronix.de, linux-rockchip@lists.infradead.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCH] clk: rockchip: rk3568: Add PLL rate for 724 MHz
Date: Sat, 4 May 2024 12:51:31 +0200 [thread overview]
Message-ID: <171481988028.3538483.628614246241628952.b4-ty@sntech.de> (raw)
In-Reply-To: <20240503153329.3906030-1-l.stach@pengutronix.de>
On Fri, 3 May 2024 17:33:29 +0200, Lucas Stach wrote:
> This rate allows to provide a low-jitter 72,4 MHz pixelclock
> for a custom eDP panel from the VPLL.
>
>
Applied, thanks!
[1/1] clk: rockchip: rk3568: Add PLL rate for 724 MHz
commit: f513991b69885025995dcb4ca75d2ee7261e1273
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
prev parent reply other threads:[~2024-05-04 10:51 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-03 15:33 [PATCH] clk: rockchip: rk3568: Add PLL rate for 724 MHz Lucas Stach
2024-05-04 10:51 ` Heiko Stuebner [this message]
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