* [PATCH] Fix AT91SAM9G20 reset
@ 2010-05-28 15:37 Peter Horton
2010-06-21 14:30 ` Lucas
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Peter Horton @ 2010-05-28 15:37 UTC (permalink / raw)
To: linux-arm-kernel
Fix AT91SAM9G20 as per the errata in the datasheet.
If the SDRAM is not cleanly shutdown before reset it can be left driving
the bus, which then stops the bootloader booting from NAND.
Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
--
Index: linux-2.6.32/arch/arm/mach-at91/Makefile
===================================================================
--- linux-2.6.32.orig/arch/arm/mach-at91/Makefile 2009-12-09 13:33:28.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/Makefile 2009-12-09 13:33:28.000000000 +0000
@@ -16,7 +16,7 @@
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
Index: linux-2.6.32/arch/arm/mach-at91/at91sam9260.c
===================================================================
--- linux-2.6.32.orig/arch/arm/mach-at91/at91sam9260.c 2009-12-03 03:51:21.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/at91sam9260.c 2009-12-09 13:45:50.000000000 +0000
@@ -25,6 +25,8 @@
#include "generic.h"
#include "clock.h"
+extern void at91sam9g20_reset(void);
+
static struct map_desc at91sam9260_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
@@ -327,7 +329,11 @@
else
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
- at91_arch_reset = at91sam9260_reset;
+ if (cpu_is_at91sam9g20())
+ at91_arch_reset = at91sam9g20_reset;
+ else
+ at91_arch_reset = at91sam9260_reset;
+
pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
Index: linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S 2009-12-09 13:33:28.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+ * (C) BitBox Ltd 2010
+ *
+ * reset AT91SAM9G20 as per errata
+ *
+ * unless the SDRAM is cleanly shutdown before we hit the
+ * reset register it can be left driving the data bus and
+ * killing the chance of a subsequent boot from NAND
+ */
+
+#define CP15_CR_I (1 << 12)
+
+#define SYS_VIRT_OFS (-0x01000000)
+
+#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
+#define SDRAMC_TR 0x0004
+#define SDRAMC_LPR 0x0010
+#define SDRAMC_LPCB_POWER_DOWN 2
+
+#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
+#define RSTC_CR 0x0000
+#define RSTC_PROCRST (1 << 0)
+#define RSTC_PERRST (1 << 2)
+#define RSTC_KEY (0xa5 << 24)
+
+ .arm
+
+ .globl at91sam9g20_reset
+
+at91sam9g20_reset: mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
+
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #CP15_CR_I
+ mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
+
+ ldr r0, =SDRAMC_BASE @ preload constants
+ ldr r1, =RSTC_BASE
+
+ mov r2, #1
+ mov r3, #SDRAMC_LPCB_POWER_DOWN
+ ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
+
+ .balign 32 @ align to cache line
+
+ str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
+ str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
+ str r4, [r1, #RSTC_CR] @ reset processor
+
+ b .
+
+/* vi:set ft=ignore ai: */
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH] Fix AT91SAM9G20 reset
2010-05-28 15:37 [PATCH] Fix AT91SAM9G20 reset Peter Horton
@ 2010-06-21 14:30 ` Lucas
2010-06-21 15:14 ` Peter Horton
2010-10-14 13:34 ` Nicolas Ferre
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Lucas @ 2010-06-21 14:30 UTC (permalink / raw)
To: linux-arm-kernel
Peter Horton <phorton <at> bitbox.co.uk> writes:
>
> Fix AT91SAM9G20 as per the errata in the datasheet.
>
> If the SDRAM is not cleanly shutdown before reset it can be left driving
> the bus, which then stops the bootloader booting from NAND.
>
> Signed-off-by: Peter Horton <phorton <at> bitbox.co.uk>
> --
>
Hi Peter,
Any Idea how to implement this for the WDT and hardware reset(NRST)?
A hardware reset sometimes still stops the bootloader booting from NAND.
Lucas
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH] Fix AT91SAM9G20 reset
2010-06-21 14:30 ` Lucas
@ 2010-06-21 15:14 ` Peter Horton
0 siblings, 0 replies; 16+ messages in thread
From: Peter Horton @ 2010-06-21 15:14 UTC (permalink / raw)
To: linux-arm-kernel
On 21/06/2010 15:30, Lucas wrote:
> Peter Horton<phorton<at> bitbox.co.uk> writes:
>
>>
>> Fix AT91SAM9G20 as per the errata in the datasheet.
>>
>> If the SDRAM is not cleanly shutdown before reset it can be left driving
>> the bus, which then stops the bootloader booting from NAND.
>>
>> Signed-off-by: Peter Horton<phorton<at> bitbox.co.uk>
>> --
>>
>
>
> Hi Peter,
>
> Any Idea how to implement this for the WDT and hardware reset(NRST)?
> A hardware reset sometimes still stops the bootloader booting from NAND.
>
Not possible to fix as far as I understand it. We've had to put down a
small DataFlash which then boots from NAND.
Turns out we needed DataFlash anyway as the Atmel boot ROM is not
compatible with newer NANDs (newer NANDs no longer guarantee block 0
without ECC and the Atmel boot ROM doesn't support ECC).
P.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] Fix AT91SAM9G20 reset
2010-05-28 15:37 [PATCH] Fix AT91SAM9G20 reset Peter Horton
2010-06-21 14:30 ` Lucas
@ 2010-10-14 13:34 ` Nicolas Ferre
2010-10-14 15:31 ` Peter Horton
2010-10-14 17:25 ` [PATCH 1/5] Fix AT91SAM9G20 reset as per the errata in the data sheet Nicolas Ferre
` (4 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Nicolas Ferre @ 2010-10-14 13:34 UTC (permalink / raw)
To: linux-arm-kernel
Le 28/05/2010 17:37, Peter Horton :
> Fix AT91SAM9G20 as per the errata in the datasheet.
>
> If the SDRAM is not cleanly shutdown before reset it can be left driving
> the bus, which then stops the bootloader booting from NAND.
>
> Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
Thanks a lot for writing this patch. I am in the process of reviewing it
and extending it to other processors.
[..]
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S 2009-12-09 13:33:28.000000000 +0000
> @@ -0,0 +1,52 @@
> +/*
> + * (C) BitBox Ltd 2010
> + *
> + * reset AT91SAM9G20 as per errata
> + *
> + * unless the SDRAM is cleanly shutdown before we hit the
> + * reset register it can be left driving the data bus and
> + * killing the chance of a subsequent boot from NAND
Can I add License sentence to this file? Like this one:
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
Best regards,
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH] Fix AT91SAM9G20 reset
2010-10-14 13:34 ` Nicolas Ferre
@ 2010-10-14 15:31 ` Peter Horton
0 siblings, 0 replies; 16+ messages in thread
From: Peter Horton @ 2010-10-14 15:31 UTC (permalink / raw)
To: linux-arm-kernel
On 14/10/2010 14:34, Nicolas Ferre wrote:
> Le 28/05/2010 17:37, Peter Horton :
>> Fix AT91SAM9G20 as per the errata in the datasheet.
>>
>> If the SDRAM is not cleanly shutdown before reset it can be left driving
>> the bus, which then stops the bootloader booting from NAND.
>>
>> Signed-off-by: Peter Horton<phorton@bitbox.co.uk>
>
> Thanks a lot for writing this patch. I am in the process of reviewing it
> and extending it to other processors.
>
> [..]
>
>> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
>> +++ linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S 2009-12-09 13:33:28.000000000 +0000
>> @@ -0,0 +1,52 @@
>> +/*
>> + * (C) BitBox Ltd 2010
>> + *
>> + * reset AT91SAM9G20 as per errata
>> + *
>> + * unless the SDRAM is cleanly shutdown before we hit the
>> + * reset register it can be left driving the data bus and
>> + * killing the chance of a subsequent boot from NAND
>
> Can I add License sentence to this file? Like this one:
>
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> * the Free Software Foundation; either version 2 of the License, or
> * (at your option) any later version.
>
No problem.
P.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/5] Fix AT91SAM9G20 reset as per the errata in the data sheet
2010-05-28 15:37 [PATCH] Fix AT91SAM9G20 reset Peter Horton
2010-06-21 14:30 ` Lucas
2010-10-14 13:34 ` Nicolas Ferre
@ 2010-10-14 17:25 ` Nicolas Ferre
2010-10-15 12:29 ` Jean-Christophe PLAGNIOL-VILLARD
2010-10-14 17:25 ` [PATCH 2/5] AT91: trivial: align comment of at91sam9g20_reset with one more tab Nicolas Ferre
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Nicolas Ferre @ 2010-10-14 17:25 UTC (permalink / raw)
To: linux-arm-kernel
From: Peter Horton <phorton@bitbox.co.uk>
If the SDRAM is not cleanly shutdown before reset it can be left driving
the bus, which then stops the bootloader booting from NAND.
Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
[nicolas.ferre at atmel.com: change file header line order]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/at91sam9260.c | 8 ++++-
arch/arm/mach-at91/at91sam9g20_reset.S | 55 ++++++++++++++++++++++++++++++++
3 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-at91/at91sam9g20_reset.S
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 88e55e3..d4bb704 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_d
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 0894f10..f884450 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -25,6 +25,8 @@
#include "generic.h"
#include "clock.h"
+extern void at91sam9g20_reset(void);
+
static struct map_desc at91sam9260_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
@@ -327,7 +329,11 @@ void __init at91sam9260_initialize(unsigned long main_clock)
else
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
- at91_arch_reset = at91sam9260_reset;
+ if (cpu_is_at91sam9g20())
+ at91_arch_reset = at91sam9g20_reset;
+ else
+ at91_arch_reset = at91sam9260_reset;
+
pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9g20_reset.S
new file mode 100644
index 0000000..f6e9b03
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g20_reset.S
@@ -0,0 +1,55 @@
+/*
+ * reset AT91SAM9G20 as per errata
+ *
+ * (C) BitBox Ltd 2010
+ *
+ * unless the SDRAM is cleanly shutdown before we hit the
+ * reset register it can be left driving the data bus and
+ * killing the chance of a subsequent boot from NAND
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#define CP15_CR_I (1 << 12)
+
+#define SYS_VIRT_OFS (-0x01000000)
+
+#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
+#define SDRAMC_TR 0x0004
+#define SDRAMC_LPR 0x0010
+#define SDRAMC_LPCB_POWER_DOWN 2
+
+#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
+#define RSTC_CR 0x0000
+#define RSTC_PROCRST (1 << 0)
+#define RSTC_PERRST (1 << 2)
+#define RSTC_KEY (0xa5 << 24)
+
+ .arm
+
+ .globl at91sam9g20_reset
+
+at91sam9g20_reset: mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
+
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #CP15_CR_I
+ mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
+
+ ldr r0, =SDRAMC_BASE @ preload constants
+ ldr r1, =RSTC_BASE
+
+ mov r2, #1
+ mov r3, #SDRAMC_LPCB_POWER_DOWN
+ ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
+
+ .balign 32 @ align to cache line
+
+ str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
+ str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
+ str r4, [r1, #RSTC_CR] @ reset processor
+
+ b .
--
1.7.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 1/5] Fix AT91SAM9G20 reset as per the errata in the data sheet
2010-10-14 17:25 ` [PATCH 1/5] Fix AT91SAM9G20 reset as per the errata in the data sheet Nicolas Ferre
@ 2010-10-15 12:29 ` Jean-Christophe PLAGNIOL-VILLARD
2010-10-19 10:05 ` Nicolas Ferre
0 siblings, 1 reply; 16+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2010-10-15 12:29 UTC (permalink / raw)
To: linux-arm-kernel
> +at91sam9g20_reset: mov r0, #0
> + mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
do we really need to flush the I-cache again
Best Regards,
J.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/5] Fix AT91SAM9G20 reset as per the errata in the data sheet
2010-10-15 12:29 ` Jean-Christophe PLAGNIOL-VILLARD
@ 2010-10-19 10:05 ` Nicolas Ferre
0 siblings, 0 replies; 16+ messages in thread
From: Nicolas Ferre @ 2010-10-19 10:05 UTC (permalink / raw)
To: linux-arm-kernel
Le 15/10/2010 14:29, Jean-Christophe PLAGNIOL-VILLARD :
>> +at91sam9g20_reset: mov r0, #0
>> + mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
> do we really need to flush the I-cache again
You are right, it is done in the calling function: arm_machine_restart().
I will correct it in the patch series.
Best regards,
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/5] AT91: trivial: align comment of at91sam9g20_reset with one more tab
2010-05-28 15:37 [PATCH] Fix AT91SAM9G20 reset Peter Horton
` (2 preceding siblings ...)
2010-10-14 17:25 ` [PATCH 1/5] Fix AT91SAM9G20 reset as per the errata in the data sheet Nicolas Ferre
@ 2010-10-14 17:25 ` Nicolas Ferre
2010-10-14 17:25 ` [PATCH 3/5] AT91: reset routine cleanup Nicolas Ferre
` (2 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Nicolas Ferre @ 2010-10-14 17:25 UTC (permalink / raw)
To: linux-arm-kernel
Preparing next patch with longer names
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/at91sam9g20_reset.S | 14 +++++++-------
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9g20_reset.S
index f6e9b03..1631c38 100644
--- a/arch/arm/mach-at91/at91sam9g20_reset.S
+++ b/arch/arm/mach-at91/at91sam9g20_reset.S
@@ -33,23 +33,23 @@
.globl at91sam9g20_reset
at91sam9g20_reset: mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
+ mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #CP15_CR_I
- mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
+ mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
- ldr r0, =SDRAMC_BASE @ preload constants
+ ldr r0, =SDRAMC_BASE @ preload constants
ldr r1, =RSTC_BASE
mov r2, #1
mov r3, #SDRAMC_LPCB_POWER_DOWN
ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
- .balign 32 @ align to cache line
+ .balign 32 @ align to cache line
- str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
- str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
- str r4, [r1, #RSTC_CR] @ reset processor
+ str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
+ str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
+ str r4, [r1, #RSTC_CR] @ reset processor
b .
--
1.7.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 3/5] AT91: reset routine cleanup
2010-05-28 15:37 [PATCH] Fix AT91SAM9G20 reset Peter Horton
` (3 preceding siblings ...)
2010-10-14 17:25 ` [PATCH 2/5] AT91: trivial: align comment of at91sam9g20_reset with one more tab Nicolas Ferre
@ 2010-10-14 17:25 ` Nicolas Ferre
2010-10-14 17:25 ` [PATCH 4/5] AT91: rename at91sam9g20_reset.S to generalize to several chips Nicolas Ferre
2010-10-14 17:25 ` [PATCH 5/5] AT91: reset: extend alternate reset procedure " Nicolas Ferre
6 siblings, 0 replies; 16+ messages in thread
From: Nicolas Ferre @ 2010-10-14 17:25 UTC (permalink / raw)
To: linux-arm-kernel
Generalize assembler reset routine to allow use on several at91sam9 chips.
This patch replace double definitions of SDRAM controller registers and RSTC
registers with use of classical header files.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/at91sam9260.c | 4 +-
arch/arm/mach-at91/at91sam9g20_reset.S | 44 ++++++++++++++-----------------
2 files changed, 22 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index f884450..dfd3529 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -25,7 +25,7 @@
#include "generic.h"
#include "clock.h"
-extern void at91sam9g20_reset(void);
+extern void at91sam9_alt_reset(void);
static struct map_desc at91sam9260_io_desc[] __initdata = {
{
@@ -330,7 +330,7 @@ void __init at91sam9260_initialize(unsigned long main_clock)
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
if (cpu_is_at91sam9g20())
- at91_arch_reset = at91sam9g20_reset;
+ at91_arch_reset = at91sam9_alt_reset;
else
at91_arch_reset = at91sam9260_reset;
diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9g20_reset.S
index 1631c38..2e5c70d 100644
--- a/arch/arm/mach-at91/at91sam9g20_reset.S
+++ b/arch/arm/mach-at91/at91sam9g20_reset.S
@@ -13,43 +13,39 @@
* (at your option) any later version.
*/
-#define CP15_CR_I (1 << 12)
-
-#define SYS_VIRT_OFS (-0x01000000)
-
-#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
-#define SDRAMC_TR 0x0004
-#define SDRAMC_LPR 0x0010
-#define SDRAMC_LPCB_POWER_DOWN 2
-
-#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
-#define RSTC_CR 0x0000
-#define RSTC_PROCRST (1 << 0)
-#define RSTC_PERRST (1 << 2)
-#define RSTC_KEY (0xa5 << 24)
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <mach/hardware.h>
+#include <mach/at91sam9_sdramc.h>
+#include <mach/at91_rstc.h>
.arm
- .globl at91sam9g20_reset
+ .globl at91sam9_alt_reset
-at91sam9g20_reset: mov r0, #0
+at91sam9_alt_reset: mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #CP15_CR_I
+ orr r0, r0, #CR_I
mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
- ldr r0, =SDRAMC_BASE @ preload constants
- ldr r1, =RSTC_BASE
+ ldr r0, .at91_va_base_sdramc @ preload constants
+ ldr r1, .at91_va_base_rstc_cr
mov r2, #1
- mov r3, #SDRAMC_LPCB_POWER_DOWN
- ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
+ mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
+ ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
.balign 32 @ align to cache line
- str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
- str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
- str r4, [r1, #RSTC_CR] @ reset processor
+ str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
+ str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
+ str r4, [r1] @ reset processor
b .
+
+.at91_va_base_sdramc:
+ .word AT91_VA_BASE_SYS + AT91_SDRAMC0
+.at91_va_base_rstc_cr:
+ .word AT91_VA_BASE_SYS + AT91_RSTC_CR
--
1.7.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 4/5] AT91: rename at91sam9g20_reset.S to generalize to several chips
2010-05-28 15:37 [PATCH] Fix AT91SAM9G20 reset Peter Horton
` (4 preceding siblings ...)
2010-10-14 17:25 ` [PATCH 3/5] AT91: reset routine cleanup Nicolas Ferre
@ 2010-10-14 17:25 ` Nicolas Ferre
2010-10-14 17:25 ` [PATCH 5/5] AT91: reset: extend alternate reset procedure " Nicolas Ferre
6 siblings, 0 replies; 16+ messages in thread
From: Nicolas Ferre @ 2010-10-14 17:25 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/Makefile | 2 +-
.../{at91sam9g20_reset.S => at91sam9_alt_reset.S} | 0
2 files changed, 1 insertions(+), 1 deletions(-)
rename arch/arm/mach-at91/{at91sam9g20_reset.S => at91sam9_alt_reset.S} (100%)
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d4bb704..15fee8b 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_d
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
similarity index 100%
rename from arch/arm/mach-at91/at91sam9g20_reset.S
rename to arch/arm/mach-at91/at91sam9_alt_reset.S
--
1.7.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 5/5] AT91: reset: extend alternate reset procedure to several chips
2010-05-28 15:37 [PATCH] Fix AT91SAM9G20 reset Peter Horton
` (5 preceding siblings ...)
2010-10-14 17:25 ` [PATCH 4/5] AT91: rename at91sam9g20_reset.S to generalize to several chips Nicolas Ferre
@ 2010-10-14 17:25 ` Nicolas Ferre
6 siblings, 0 replies; 16+ messages in thread
From: Nicolas Ferre @ 2010-10-14 17:25 UTC (permalink / raw)
To: linux-arm-kernel
Several at91sam9 chips need the alternate reset procedure to be sure to halt
SDRAM smoothly before resetting the chip.
This is an extension of previous patch "Fix AT91SAM9G20 reset" to all chips
affected.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/Makefile | 10 +++++-----
arch/arm/mach-at91/at91sam9260.c | 13 +------------
arch/arm/mach-at91/at91sam9261.c | 7 +------
arch/arm/mach-at91/at91sam9263.c | 7 +------
arch/arm/mach-at91/at91sam9rl.c | 7 +------
arch/arm/mach-at91/generic.h | 3 +++
6 files changed, 12 insertions(+), 35 deletions(-)
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 15fee8b..428266f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -11,11 +11,11 @@ obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
# CPU-specific support
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
+obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
+obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
+obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o
+obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index dfd3529..195208b 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -25,8 +25,6 @@
#include "generic.h"
#include "clock.h"
-extern void at91sam9_alt_reset(void);
-
static struct map_desc at91sam9260_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
@@ -281,11 +279,6 @@ static struct at91_gpio_bank at91sam9260_gpio[] = {
}
};
-static void at91sam9260_reset(void)
-{
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
static void at91sam9260_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
@@ -329,11 +322,7 @@ void __init at91sam9260_initialize(unsigned long main_clock)
else
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
- if (cpu_is_at91sam9g20())
- at91_arch_reset = at91sam9_alt_reset;
- else
- at91_arch_reset = at91sam9260_reset;
-
+ at91_arch_reset = at91sam9_alt_reset;
pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 4ecf379..fcad886 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -257,11 +257,6 @@ static struct at91_gpio_bank at91sam9261_gpio[] = {
}
};
-static void at91sam9261_reset(void)
-{
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
static void at91sam9261_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
@@ -283,7 +278,7 @@ void __init at91sam9261_initialize(unsigned long main_clock)
iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
- at91_arch_reset = at91sam9261_reset;
+ at91_arch_reset = at91sam9_alt_reset;
pm_power_off = at91sam9261_poweroff;
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 942792d..249f900 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -269,11 +269,6 @@ static struct at91_gpio_bank at91sam9263_gpio[] = {
}
};
-static void at91sam9263_reset(void)
-{
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
static void at91sam9263_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
@@ -289,7 +284,7 @@ void __init at91sam9263_initialize(unsigned long main_clock)
/* Map peripherals */
iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
- at91_arch_reset = at91sam9263_reset;
+ at91_arch_reset = at91sam9_alt_reset;
pm_power_off = at91sam9263_poweroff;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 211c5c1..6a9d24e 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -242,11 +242,6 @@ static struct at91_gpio_bank at91sam9rl_gpio[] = {
}
};
-static void at91sam9rl_reset(void)
-{
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
static void at91sam9rl_poweroff(void)
{
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
@@ -281,7 +276,7 @@ void __init at91sam9rl_initialize(unsigned long main_clock)
/* Map SRAM */
iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
- at91_arch_reset = at91sam9rl_reset;
+ at91_arch_reset = at91sam9_alt_reset;
pm_power_off = at91sam9rl_poweroff;
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 65c3dc5..0c66deb 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -46,6 +46,9 @@ extern void __init at91_clock_associate(const char *id, struct device *dev, cons
extern void at91_irq_suspend(void);
extern void at91_irq_resume(void);
+/* reset */
+extern void at91sam9_alt_reset(void);
+
/* GPIO */
#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
--
1.7.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH] Fix AT91SAM9G20 reset
@ 2010-04-13 8:31 Peter Horton
0 siblings, 0 replies; 16+ messages in thread
From: Peter Horton @ 2010-04-13 8:31 UTC (permalink / raw)
To: linux-arm-kernel
Fix AT91SAM9G20 reset as per the errata in the data sheet.
If the SDRAM is not cleanly shutdown before reset it can be left driving
the bus, which then stops the bootloader booting from NAND.
Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
--
Index: linux-2.6.32/arch/arm/mach-at91/Makefile
===================================================================
--- linux-2.6.32.orig/arch/arm/mach-at91/Makefile 2009-12-15 09:53:27.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/Makefile 2009-12-15 09:53:27.000000000 +0000
@@ -16,7 +16,7 @@
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
Index: linux-2.6.32/arch/arm/mach-at91/at91sam9260.c
===================================================================
--- linux-2.6.32.orig/arch/arm/mach-at91/at91sam9260.c 2009-12-03 03:51:21.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/at91sam9260.c 2009-12-15 09:53:27.000000000 +0000
@@ -25,6 +25,8 @@
#include "generic.h"
#include "clock.h"
+extern void at91sam9g20_reset(void);
+
static struct map_desc at91sam9260_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
@@ -327,7 +329,11 @@
else
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
- at91_arch_reset = at91sam9260_reset;
+ if (cpu_is_at91sam9g20())
+ at91_arch_reset = at91sam9g20_reset;
+ else
+ at91_arch_reset = at91sam9260_reset;
+
pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
Index: linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S 2009-12-15 09:55:17.000000000 +0000
@@ -0,0 +1,50 @@
+/*
+ * (C) BitBox Ltd 2009
+ *
+ * reset AT91SAM9G20 as per errata
+ *
+ * unless the SDRAM is cleanly shutdown before we hit the
+ * reset register it can be left driving the data bus and
+ * killing the chance of a subsequent boot from NAND
+ */
+
+#define CP15_CR_I (1 << 12)
+
+#define SYS_VIRT_OFS (-0x01000000)
+
+#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
+#define SDRAMC_TR 0x0004
+#define SDRAMC_LPR 0x0010
+#define SDRAMC_LPCB_POWER_DOWN 2
+
+#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
+#define RSTC_CR 0x0000
+#define RSTC_PROCRST (1 << 0)
+#define RSTC_PERRST (1 << 2)
+#define RSTC_KEY (0xa5 << 24)
+
+ .arm
+
+ .globl at91sam9g20_reset
+
+at91sam9g20_reset: mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
+
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #CP15_CR_I
+ mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
+
+ ldr r0, =SDRAMC_BASE @ preload constants
+ ldr r1, =RSTC_BASE
+
+ mov r2, #1
+ mov r3, #SDRAMC_LPCB_POWER_DOWN
+ ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
+
+ .balign 32 @ align to cache line
+
+ str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
+ str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
+ str r4, [r1, #RSTC_CR] @ reset processor
+
+ b .
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH] Fix AT91SAM9G20 reset
@ 2009-12-15 9:59 Peter Horton
0 siblings, 0 replies; 16+ messages in thread
From: Peter Horton @ 2009-12-15 9:59 UTC (permalink / raw)
To: linux-arm-kernel
Fix AT91SAM9G20 reset as per the errata in the data sheet.
If the SDRAM is not cleanly shutdown before reset it can be left driving
the bus, which then stops the bootloader booting from NAND.
Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
--
Index: linux-2.6.32/arch/arm/mach-at91/Makefile
===================================================================
--- linux-2.6.32.orig/arch/arm/mach-at91/Makefile 2009-12-15 09:53:27.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/Makefile 2009-12-15 09:53:27.000000000 +0000
@@ -16,7 +16,7 @@
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
Index: linux-2.6.32/arch/arm/mach-at91/at91sam9260.c
===================================================================
--- linux-2.6.32.orig/arch/arm/mach-at91/at91sam9260.c 2009-12-03 03:51:21.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/at91sam9260.c 2009-12-15 09:53:27.000000000 +0000
@@ -25,6 +25,8 @@
#include "generic.h"
#include "clock.h"
+extern void at91sam9g20_reset(void);
+
static struct map_desc at91sam9260_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
@@ -327,7 +329,11 @@
else
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
- at91_arch_reset = at91sam9260_reset;
+ if (cpu_is_at91sam9g20())
+ at91_arch_reset = at91sam9g20_reset;
+ else
+ at91_arch_reset = at91sam9260_reset;
+
pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
Index: linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S 2009-12-15 09:55:17.000000000 +0000
@@ -0,0 +1,50 @@
+/*
+ * (C) BitBox Ltd 2009
+ *
+ * reset AT91SAM9G20 as per errata
+ *
+ * unless the SDRAM is cleanly shutdown before we hit the
+ * reset register it can be left driving the data bus and
+ * killing the chance of a subsequent boot from NAND
+ */
+
+#define CP15_CR_I (1 << 12)
+
+#define SYS_VIRT_OFS (-0x01000000)
+
+#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
+#define SDRAMC_TR 0x0004
+#define SDRAMC_LPR 0x0010
+#define SDRAMC_LPCB_POWER_DOWN 2
+
+#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
+#define RSTC_CR 0x0000
+#define RSTC_PROCRST (1 << 0)
+#define RSTC_PERRST (1 << 2)
+#define RSTC_KEY (0xa5 << 24)
+
+ .arm
+
+ .globl at91sam9g20_reset
+
+at91sam9g20_reset: mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
+
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #CP15_CR_I
+ mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
+
+ ldr r0, =SDRAMC_BASE @ preload constants
+ ldr r1, =RSTC_BASE
+
+ mov r2, #1
+ mov r3, #SDRAMC_LPCB_POWER_DOWN
+ ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
+
+ .balign 32 @ align to cache line
+
+ str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
+ str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
+ str r4, [r1, #RSTC_CR] @ reset processor
+
+ b .
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH] Fix AT91SAM9G20 reset
@ 2009-12-09 13:50 Peter Horton
2009-12-09 14:09 ` Paulius Zaleckas
0 siblings, 1 reply; 16+ messages in thread
From: Peter Horton @ 2009-12-09 13:50 UTC (permalink / raw)
To: linux-arm-kernel
Fix AT91SAM9G20 reset as per the errata in the data sheet.
If the SDRAM is not cleanly shutdown before reset it can be left driving
the bus, which then stops the bootloader booting from NAND.
Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
--
Index: linux-2.6.32/arch/arm/mach-at91/Makefile
===================================================================
--- linux-2.6.32.orig/arch/arm/mach-at91/Makefile 2009-12-09 13:33:28.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/Makefile 2009-12-09 13:33:28.000000000 +0000
@@ -16,7 +16,7 @@
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9g20_reset.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
Index: linux-2.6.32/arch/arm/mach-at91/at91sam9260.c
===================================================================
--- linux-2.6.32.orig/arch/arm/mach-at91/at91sam9260.c 2009-12-03 03:51:21.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/at91sam9260.c 2009-12-09 13:45:50.000000000 +0000
@@ -25,6 +25,8 @@
#include "generic.h"
#include "clock.h"
+extern void at91sam9g20_reset(void);
+
static struct map_desc at91sam9260_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
@@ -327,7 +329,11 @@
else
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
- at91_arch_reset = at91sam9260_reset;
+ if (cpu_is_at91sam9g20())
+ at91_arch_reset = at91sam9g20_reset;
+ else
+ at91_arch_reset = at91sam9260_reset;
+
pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
Index: linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S 2009-12-09 13:33:28.000000000 +0000
@@ -0,0 +1,52 @@
+/*
+ * (C) BitBox Ltd 2009
+ *
+ * reset AT91SAM9G20 as per errata
+ *
+ * unless the SDRAM is cleanly shutdown before we hit the
+ * reset register it can be left driving the data bus and
+ * killing the chance of a subsequent boot from NAND
+ */
+
+#define CP15_CR_I (1 << 12)
+
+#define SYS_VIRT_OFS (-0x01000000)
+
+#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
+#define SDRAMC_TR 0x0004
+#define SDRAMC_LPR 0x0010
+#define SDRAMC_LPCB_POWER_DOWN 2
+
+#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
+#define RSTC_CR 0x0000
+#define RSTC_PROCRST (1 << 0)
+#define RSTC_PERRST (1 << 2)
+#define RSTC_KEY (0xa5 << 24)
+
+ .arm
+
+ .globl at91sam9g20_reset
+
+at91sam9g20_reset: mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
+
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #CP15_CR_I
+ mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
+
+ ldr r0, =SDRAMC_BASE @ preload constants
+ ldr r1, =RSTC_BASE
+
+ mov r2, #1
+ mov r3, #SDRAMC_LPCB_POWER_DOWN
+ ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
+
+ .balign 32 @ align to cache line
+
+ str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
+ str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
+ str r4, [r1, #RSTC_CR] @ reset processor
+
+ b .
+
+/* vi:set ft=ignore ai: */
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH] Fix AT91SAM9G20 reset
2009-12-09 13:50 Peter Horton
@ 2009-12-09 14:09 ` Paulius Zaleckas
0 siblings, 0 replies; 16+ messages in thread
From: Paulius Zaleckas @ 2009-12-09 14:09 UTC (permalink / raw)
To: linux-arm-kernel
On 12/09/2009 03:50 PM, Peter Horton wrote:
> Fix AT91SAM9G20 reset as per the errata in the data sheet.
>
> If the SDRAM is not cleanly shutdown before reset it can be left driving
> the bus, which then stops the bootloader booting from NAND.
>
> Signed-off-by: Peter Horton<phorton@bitbox.co.uk>
> --
>
[...]
> Index: linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ linux-2.6.32/arch/arm/mach-at91/at91sam9g20_reset.S 2009-12-09 13:33:28.000000000 +0000
> @@ -0,0 +1,52 @@
> +/*
> + * (C) BitBox Ltd 2009
> + *
> + * reset AT91SAM9G20 as per errata
> + *
> + * unless the SDRAM is cleanly shutdown before we hit the
> + * reset register it can be left driving the data bus and
> + * killing the chance of a subsequent boot from NAND
> + */
> +
> +#define CP15_CR_I (1<< 12)
> +
> +#define SYS_VIRT_OFS (-0x01000000)
> +
> +#define SDRAMC_BASE (SYS_VIRT_OFS + 0xffffea00)
> +#define SDRAMC_TR 0x0004
> +#define SDRAMC_LPR 0x0010
> +#define SDRAMC_LPCB_POWER_DOWN 2
> +
> +#define RSTC_BASE (SYS_VIRT_OFS + 0xfffffd00)
> +#define RSTC_CR 0x0000
> +#define RSTC_PROCRST (1<< 0)
> +#define RSTC_PERRST (1<< 2)
> +#define RSTC_KEY (0xa5<< 24)
> +
> + .arm
> +
> + .globl at91sam9g20_reset
> +
> +at91sam9g20_reset: mov r0, #0
> + mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
> +
> + mrc p15, 0, r0, c1, c0, 0
> + orr r0, r0, #CP15_CR_I
> + mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
> +
> + ldr r0, =SDRAMC_BASE @ preload constants
> + ldr r1, =RSTC_BASE
> +
> + mov r2, #1
> + mov r3, #SDRAMC_LPCB_POWER_DOWN
> + ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
> +
> + .balign 32 @ align to cache line
> +
> + str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
> + str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
> + str r4, [r1, #RSTC_CR] @ reset processor
> +
> + b .
> +
> +/* vi:set ft=ignore ai: */
Please remove the vi bits.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2010-10-19 10:05 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-05-28 15:37 [PATCH] Fix AT91SAM9G20 reset Peter Horton
2010-06-21 14:30 ` Lucas
2010-06-21 15:14 ` Peter Horton
2010-10-14 13:34 ` Nicolas Ferre
2010-10-14 15:31 ` Peter Horton
2010-10-14 17:25 ` [PATCH 1/5] Fix AT91SAM9G20 reset as per the errata in the data sheet Nicolas Ferre
2010-10-15 12:29 ` Jean-Christophe PLAGNIOL-VILLARD
2010-10-19 10:05 ` Nicolas Ferre
2010-10-14 17:25 ` [PATCH 2/5] AT91: trivial: align comment of at91sam9g20_reset with one more tab Nicolas Ferre
2010-10-14 17:25 ` [PATCH 3/5] AT91: reset routine cleanup Nicolas Ferre
2010-10-14 17:25 ` [PATCH 4/5] AT91: rename at91sam9g20_reset.S to generalize to several chips Nicolas Ferre
2010-10-14 17:25 ` [PATCH 5/5] AT91: reset: extend alternate reset procedure " Nicolas Ferre
-- strict thread matches above, loose matches on Subject: below --
2010-04-13 8:31 [PATCH] Fix AT91SAM9G20 reset Peter Horton
2009-12-15 9:59 Peter Horton
2009-12-09 13:50 Peter Horton
2009-12-09 14:09 ` Paulius Zaleckas
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