[PATCH] irqchip/gic-v4.1:Check whether indirect table is supported in allocate_vpe_l1_table

From: Nianyao Tang <tangnianyao@huawei.com>
To: <maz@kernel.org>, <tglx@linutronix.de>,
	<"linux-kernel@vger.kernel.orgstefanha"@redhat.com>,
	<linux-arm-kernel@lists.infradead.org>
Cc: <tangnianyao@huawei.com>, <guoyang2@huawei.com>,
	<wangwudi@hisilicon.com>
Subject: [PATCH] irqchip/gic-v4.1:Check whether indirect table is supported in allocate_vpe_l1_table
Date: Mon, 22 Jan 2024 16:06:07 +0000	[thread overview]
Message-ID: <20240122160607.1078960-1-tangnianyao@huawei.com> (raw)

In allocate_vpe_l1_table, when we fail to inherit VPE table from other
redistributors or ITSs, and we allocate a new vpe table for current common 
affinity field without checking whether indirect table is supported.
Let's fix it.

Signed-off-by: Nianyao Tang <tangnianyao@huawei.com>
---
 drivers/irqchip/irq-gic-v3-its.c   | 28 ++++++++++++++++++++++------
 include/linux/irqchip/arm-gic-v3.h |  1 +
 2 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index d097001c1e3e..4146d1e285ec 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2836,6 +2836,7 @@ static int allocate_vpe_l1_table(void)
 	unsigned int psz = SZ_64K;
 	unsigned int np, epp, esz;
 	struct page *page;
+	bool indirect = false;
 
 	if (!gic_rdists->has_rvpeid)
 		return 0;
@@ -2890,6 +2891,12 @@ static int allocate_vpe_l1_table(void)
 		break;
 	}
 
+	/* probe the indirect */
+	val = GICR_VPROPBASER_4_1_INDIRECT;
+	gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
+	val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
+	indirect = !!(val & GICR_VPROPBASER_4_1_INDIRECT);
+
 	/*
 	 * Start populating the register from scratch, including RO fields
 	 * (which we want to print in debug cases...)
@@ -2907,15 +2914,24 @@ static int allocate_vpe_l1_table(void)
 	 * as indirect and compute the number of required L1 pages.
 	 */
 	if (epp < ITS_MAX_VPEID) {
-		int nl2;
+		if (indirect) {
+			int nl2;
 
-		val |= GICR_VPROPBASER_4_1_INDIRECT;
+			val |= GICR_VPROPBASER_4_1_INDIRECT;
 
-		/* Number of L2 pages required to cover the VPEID space */
-		nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
+			/* Number of L2 pages required to cover the VPEID space */
+			nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
 
-		/* Number of L1 pages to point to the L2 pages */
-		npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
+			/* Number of L1 pages to point to the L2 pages */
+			npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
+		} else {
+			npg = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
+			if (npg > GICR_VPROPBASER_PAGES_MAX) {
+				pr_warn("GICR_VPROPBASER pages too large, reduce %llu->%u\n",
+					npg, GICR_VPROPBASER_PAGES_MAX);
+				npg = GICR_VPROPBASER_PAGES_MAX;
+			}
+		}
 	} else {
 		npg = 1;
 	}
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 728691365464..ace37dfbff20 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -303,6 +303,7 @@
 #define GICR_VPROPBASER_4_1_Z		(1ULL << 52)
 #define GICR_VPROPBASER_4_1_ADDR	GENMASK_ULL(51, 12)
 #define GICR_VPROPBASER_4_1_SIZE	GENMASK_ULL(6, 0)
+#define GICR_VPROPBASER_PAGES_MAX  128
 
 #define GICR_VPENDBASER			0x0078
 
-- 
2.30.0


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