From: Dmitry Rokosov <ddrokosov@salutedevices.com>
To: <neil.armstrong@linaro.org>, <jbrunet@baylibre.com>,
<mturquette@baylibre.com>, <sboyd@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<khilman@baylibre.com>, <martin.blumenstingl@googlemail.com>
Cc: <kernel@salutedevices.com>, <rockosov@gmail.com>,
<linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Dmitry Rokosov <ddrokosov@salutedevices.com>
Subject: [PATCH v1 4/6] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input
Date: Fri, 29 Mar 2024 23:58:44 +0300 [thread overview]
Message-ID: <20240329205904.25002-5-ddrokosov@salutedevices.com> (raw)
In-Reply-To: <20240329205904.25002-1-ddrokosov@salutedevices.com>
The clock 'sys_pll_div16' is one of the parents of the GEN clock. It is
generated in the A1 PLL clock controller with a fixed factor.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
---
drivers/clk/meson/a1-peripherals.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c
index 621af1e6e4b2..3c4452f2b146 100644
--- a/drivers/clk/meson/a1-peripherals.c
+++ b/drivers/clk/meson/a1-peripherals.c
@@ -747,13 +747,13 @@ static struct clk_regmap fclk_div2_divn = {
};
/*
- * the index 2 is sys_pll_div16, it will be implemented in the CPU clock driver,
* the index 4 is the clock measurement source, it's not supported yet
*/
-static u32 gen_table[] = { 0, 1, 3, 5, 6, 7, 8 };
+static u32 gen_table[] = { 0, 1, 2, 3, 5, 6, 7, 8 };
static const struct clk_parent_data gen_parent_data[] = {
{ .fw_name = "xtal", },
{ .hw = &rtc.hw },
+ { .fw_name = "sys_pll_div16", },
{ .fw_name = "hifi_pll", },
{ .fw_name = "fclk_div2", },
{ .fw_name = "fclk_div3", },
--
2.43.0
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next prev parent reply other threads:[~2024-03-29 20:59 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-29 20:58 [PATCH v1 0/6] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver Dmitry Rokosov
2024-03-29 20:58 ` [PATCH v1 1/6] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Dmitry Rokosov
2024-04-01 14:20 ` Rob Herring
2024-04-01 17:22 ` Dmitry Rokosov
2024-03-29 20:58 ` [PATCH v1 2/6] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Dmitry Rokosov
2024-04-02 9:00 ` Jerome Brunet
2024-04-02 12:15 ` Dmitry Rokosov
2024-04-02 14:27 ` Jerome Brunet
2024-04-02 15:00 ` Dmitry Rokosov
2024-03-29 20:58 ` Dmitry Rokosov [this message]
2024-03-29 20:58 ` [PATCH v1 5/6] dt-bindings: clock: meson: add A1 CPU clock controller bindings Dmitry Rokosov
2024-04-01 14:57 ` Rob Herring
2024-03-29 20:58 ` [PATCH v1 6/6] clk: meson: a1: add Amlogic A1 CPU clock controller driver Dmitry Rokosov
2024-03-31 21:40 ` Martin Blumenstingl
2024-04-01 17:12 ` Dmitry Rokosov
2024-04-02 9:27 ` Jerome Brunet
2024-04-02 11:43 ` Dmitry Rokosov
2024-04-02 9:35 ` Jerome Brunet
2024-04-02 11:05 ` Dmitry Rokosov
2024-04-02 14:11 ` Jerome Brunet
2024-04-02 16:11 ` Dmitry Rokosov
2024-04-02 16:17 ` Jerome Brunet
[not found] ` <20240329205904.25002-4-ddrokosov@salutedevices.com>
2024-04-01 14:21 ` [PATCH v1 3/6] dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input Rob Herring
2024-04-01 17:19 ` Dmitry Rokosov
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