From: Jerome Brunet <jbrunet@baylibre.com>
To: Conor Dooley <conor@kernel.org>
Cc: Dmitry Rokosov <ddrokosov@salutedevices.com>,
neil.armstrong@linaro.org, jbrunet@baylibre.com,
mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com,
martin.blumenstingl@googlemail.com, jian.hu@amlogic.com,
kernel@sberdevices.ru, rockosov@gmail.com,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input
Date: Mon, 13 May 2024 14:02:21 +0200 [thread overview]
Message-ID: <1jo799zzn5.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20240511-courier-afflicted-e351af5cded2@spud>
On Sat 11 May 2024 at 14:03, Conor Dooley <conor@kernel.org> wrote:
> [[PGP Signed Part:Undecided]]
> On Fri, May 10, 2024 at 12:08:56PM +0300, Dmitry Rokosov wrote:
>> The 'sys_pll_div16' input clock is used as one of the sources for the
>> GEN clock.
>>
>> Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
>
> Provided that this new clock is optional in the driver,
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
The way CCF works, it is not going to crash if DT does not have this.
It will be viewed as non-connected input, in a way
>
> Cheers,
> Conor.
>
>> ---
>> .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 7 +++++--
>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
>> index 6d84cee1bd75..11862746ba44 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
>> @@ -30,6 +30,7 @@ properties:
>> - description: input fixed pll div7
>> - description: input hifi pll
>> - description: input oscillator (usually at 24MHz)
>> + - description: input sys pll div16
>>
>> clock-names:
>> items:
>> @@ -39,6 +40,7 @@ properties:
>> - const: fclk_div7
>> - const: hifi_pll
>> - const: xtal
>> + - const: sys_pll_div16
>>
>> required:
>> - compatible
>> @@ -65,9 +67,10 @@ examples:
>> <&clkc_pll CLKID_FCLK_DIV5>,
>> <&clkc_pll CLKID_FCLK_DIV7>,
>> <&clkc_pll CLKID_HIFI_PLL>,
>> - <&xtal>;
>> + <&xtal>,
>> + <&clkc_pll CLKID_SYS_PLL_DIV16>;
>> clock-names = "fclk_div2", "fclk_div3",
>> "fclk_div5", "fclk_div7",
>> - "hifi_pll", "xtal";
>> + "hifi_pll", "xtal", "sys_pll_div16";
>> };
>> };
>> --
>> 2.43.0
>>
>>
>
> [[End of PGP Signed Part]]
--
Jerome
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next prev parent reply other threads:[~2024-05-13 12:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 9:08 [PATCH v2 0/7] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 1/7] clk: meson: introduce 'INIT_ONCE' flag to eliminate init for enabled PLL Dmitry Rokosov
2024-05-13 12:44 ` Jerome Brunet
2024-05-13 21:47 ` Dmitry Rokosov
2024-05-15 13:12 ` Jerome Brunet
2024-05-10 9:08 ` [PATCH v2 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Dmitry Rokosov
2024-05-11 13:08 ` Conor Dooley
2024-05-13 9:18 ` Dmitry Rokosov
2024-05-13 15:48 ` Conor Dooley
2024-05-13 18:30 ` Dmitry Rokosov
2024-05-15 13:15 ` Jerome Brunet
2024-05-13 12:04 ` Jerome Brunet
2024-05-13 15:42 ` Conor Dooley
2024-05-10 9:08 ` [PATCH v2 3/7] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Dmitry Rokosov
2024-05-13 12:48 ` Jerome Brunet
2024-05-13 21:25 ` Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input Dmitry Rokosov
2024-05-11 13:03 ` Conor Dooley
2024-05-13 12:02 ` Jerome Brunet [this message]
2024-05-10 9:08 ` [PATCH v2 5/7] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 6/7] dt-bindings: clock: meson: add A1 CPU clock controller bindings Dmitry Rokosov
2024-05-10 9:08 ` [PATCH v2 7/7] clk: meson: a1: add Amlogic A1 CPU clock controller driver Dmitry Rokosov
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