KVM ARM Archive mirror
 help / color / mirror / Atom feed
From: Haibo Xu <haibo1.xu@intel.com>
Cc: xiaobo55x@gmail.com, ajones@ventanamicro.com,
	Haibo Xu <haibo1.xu@intel.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Shuah Khan <shuah@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Oliver Upton <oliver.upton@linux.dev>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Mayuresh Chitale <mchitale@ventanamicro.com>,
	wchen <waylingii@gmail.com>,
	Greentime Hu <greentime.hu@sifive.com>,
	Jisheng Zhang <jszhang@kernel.org>,
	Samuel Holland <samuel@sholland.org>,
	Minda Chen <minda.chen@starfivetech.com>,
	Sean Christopherson <seanjc@google.com>,
	Peter Xu <peterx@redhat.com>, Like Xu <likexu@tencent.com>,
	Vipin Sharma <vipinsh@google.com>, Thomas Huth <thuth@redhat.com>,
	Aaron Lewis <aaronlewis@google.com>,
	Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	kvm@vger.kernel.org, linux-kselftest@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	kvm-riscv@lists.infradead.org
Subject: [PATCH v5 00/12] RISCV: Add kvm Sstc timer selftests
Date: Mon, 22 Jan 2024 17:58:30 +0800	[thread overview]
Message-ID: <cover.1705916069.git.haibo1.xu@intel.com> (raw)

The RISC-V arch_timer selftests is used to validate Sstc timer
functionality in a guest, which sets up periodic timer interrupts
and check the basic interrupt status upon its receipt.

This KVM selftests was ported from aarch64 arch_timer and tested
with Linux v6.7-rc8 on a Qemu riscv64 virt machine.

---
Changed since v4:
  * Rebased to Linux 6.7-rc8
  * Added new patch(2/12) to clean up the data type in struct test_args
  * Re-ordered patch(11/11) in v4 to patch(3/12)
  * Changed the timer_err_margin_us type from int to uint32_t

Haibo Xu (11):
  KVM: arm64: selftests: Data type cleanup for arch_timer test
  KVM: arm64: selftests: Enable tuning of error margin in arch_timer
    test
  KVM: arm64: selftests: Split arch_timer test code
  KVM: selftests: Add CONFIG_64BIT definition for the build
  tools: riscv: Add header file csr.h
  tools: riscv: Add header file vdso/processor.h
  KVM: riscv: selftests: Switch to use macro from csr.h
  KVM: riscv: selftests: Add exception handling support
  KVM: riscv: selftests: Add guest helper to get vcpu id
  KVM: riscv: selftests: Change vcpu_has_ext to a common function
  KVM: riscv: selftests: Add sstc timer test

Paolo Bonzini (1):
  selftests/kvm: Fix issues with $(SPLIT_TESTS)

 tools/arch/riscv/include/asm/csr.h            | 541 ++++++++++++++++++
 tools/arch/riscv/include/asm/vdso/processor.h |  32 ++
 tools/testing/selftests/kvm/Makefile          |  27 +-
 .../selftests/kvm/aarch64/arch_timer.c        | 295 +---------
 tools/testing/selftests/kvm/arch_timer.c      | 259 +++++++++
 .../selftests/kvm/include/aarch64/processor.h |   4 -
 .../selftests/kvm/include/kvm_util_base.h     |   9 +
 .../selftests/kvm/include/riscv/arch_timer.h  |  71 +++
 .../selftests/kvm/include/riscv/processor.h   |  65 ++-
 .../testing/selftests/kvm/include/test_util.h |   2 +
 .../selftests/kvm/include/timer_test.h        |  45 ++
 .../selftests/kvm/lib/riscv/handlers.S        | 101 ++++
 .../selftests/kvm/lib/riscv/processor.c       |  87 +++
 .../testing/selftests/kvm/riscv/arch_timer.c  | 111 ++++
 .../selftests/kvm/riscv/get-reg-list.c        |  11 +-
 15 files changed, 1353 insertions(+), 307 deletions(-)
 create mode 100644 tools/arch/riscv/include/asm/csr.h
 create mode 100644 tools/arch/riscv/include/asm/vdso/processor.h
 create mode 100644 tools/testing/selftests/kvm/arch_timer.c
 create mode 100644 tools/testing/selftests/kvm/include/riscv/arch_timer.h
 create mode 100644 tools/testing/selftests/kvm/include/timer_test.h
 create mode 100644 tools/testing/selftests/kvm/lib/riscv/handlers.S
 create mode 100644 tools/testing/selftests/kvm/riscv/arch_timer.c

-- 
2.34.1


             reply	other threads:[~2024-01-22  9:45 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-22  9:58 Haibo Xu [this message]
2024-01-22  9:58 ` [PATCH v5 01/12] selftests/kvm: Fix issues with $(SPLIT_TESTS) Haibo Xu
2024-01-22  9:58 ` [PATCH v5 02/12] KVM: arm64: selftests: Data type cleanup for arch_timer test Haibo Xu
2024-01-22 12:21   ` Andrew Jones
2024-01-22 13:08     ` Haibo Xu
2024-01-22  9:58 ` [PATCH v5 03/12] KVM: arm64: selftests: Enable tuning of error margin in " Haibo Xu
2024-01-22  9:58 ` [PATCH v5 04/12] KVM: arm64: selftests: Split arch_timer test code Haibo Xu
2024-01-22  9:58 ` [PATCH v5 05/12] KVM: selftests: Add CONFIG_64BIT definition for the build Haibo Xu
2024-01-22  9:58 ` [PATCH v5 06/12] tools: riscv: Add header file csr.h Haibo Xu
2024-01-22  9:58 ` [PATCH v5 07/12] tools: riscv: Add header file vdso/processor.h Haibo Xu
2024-01-22  9:58 ` [PATCH v5 08/12] KVM: riscv: selftests: Switch to use macro from csr.h Haibo Xu
2024-01-22  9:58 ` [PATCH v5 09/12] KVM: riscv: selftests: Add exception handling support Haibo Xu
2024-01-22  9:58 ` [PATCH v5 10/12] KVM: riscv: selftests: Add guest helper to get vcpu id Haibo Xu
2024-01-22  9:58 ` [PATCH v5 11/12] KVM: riscv: selftests: Change vcpu_has_ext to a common function Haibo Xu
2024-02-20 23:03   ` Atish Patra
2024-02-21  2:13     ` Haibo Xu
2024-02-21  8:37       ` Atish Patra
2024-02-21 13:08         ` Haibo Xu
2024-02-21 20:29           ` Atish Patra
2024-02-26  5:19         ` Anup Patel
2024-02-26  5:47           ` Haibo Xu
2024-01-22  9:58 ` [PATCH v5 12/12] KVM: riscv: selftests: Add sstc timer test Haibo Xu
2024-02-05 13:10 ` [PATCH v5 00/12] RISCV: Add kvm Sstc timer selftests Haibo Xu
2024-02-05 16:24   ` Marc Zyngier
2024-02-06  1:32     ` Haibo Xu
2024-02-12 12:23 ` Anup Patel
2024-02-18  6:41   ` Haibo Xu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=cover.1705916069.git.haibo1.xu@intel.com \
    --to=haibo1.xu@intel.com \
    --cc=aaronlewis@google.com \
    --cc=ajones@ventanamicro.com \
    --cc=anup@brainfault.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=atishp@atishpatra.org \
    --cc=conor.dooley@microchip.com \
    --cc=greentime.hu@sifive.com \
    --cc=guoren@kernel.org \
    --cc=james.morse@arm.com \
    --cc=jszhang@kernel.org \
    --cc=kvm-riscv@lists.infradead.org \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.linux.dev \
    --cc=likexu@tencent.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-kselftest@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=maciej.wieczor-retman@intel.com \
    --cc=maz@kernel.org \
    --cc=mchitale@ventanamicro.com \
    --cc=minda.chen@starfivetech.com \
    --cc=oliver.upton@linux.dev \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=pbonzini@redhat.com \
    --cc=peterx@redhat.com \
    --cc=samuel@sholland.org \
    --cc=seanjc@google.com \
    --cc=shuah@kernel.org \
    --cc=suzuki.poulose@arm.com \
    --cc=thuth@redhat.com \
    --cc=vipinsh@google.com \
    --cc=waylingii@gmail.com \
    --cc=xiaobo55x@gmail.com \
    --cc=yuzenghui@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).