From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
To: Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Cc: James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Subject: [PATCH RFC] KVM: arm64: allow ID_MMFR4_EL1 to be writable
Date: Wed, 01 May 2024 18:06:51 +0100 [thread overview]
Message-ID: <E1s2DPv-00AhaA-Ra@rmk-PC.armlinux.org.uk> (raw)
Between 5.4 and 5.15, the guests view of HPDS, CnP, XNX and AC2
changed their value on the same Neoverse N1 r3p1 hardware which makes
migrating between these kernels on the host problematical.
We already permit changing HPDS in AA64MMFR1_EL1 and CnP in
AA64MMFR2_EL1. We also allow LSM as we allow that in AA64MMFR2_EL1,
so this patch includes support for that even though it isn't required.
Discussing with Marc Zygnier, AC2 should also be fine to be writable,
even though we don't inject an UNDEF if the guest accesses those
registers.
The only questionable one is XNX, execute-never control distinction,
which is also in AA64MMFR1_EL1 but we don't allow to be changed there.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
arch/arm64/kvm/sys_regs.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 0cc289b17665..f306b38ec341 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -2116,6 +2116,16 @@ static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu,
.val = mask, \
}
+/* sys_reg_desc initialiser for writable AA32 ID registers */
+#define AA32_ID_WRITABLE(name, mask) { \
+ ID_DESC(name), \
+ .set_user = set_id_reg, \
+ .visibility = aa32_id_visibility, \
+ .reset = kvm_read_sanitised_id_reg, \
+ .val = mask, \
+}
+
+
/*
* sys_reg_desc initialiser for architecturally unallocated cpufeature ID
* register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
@@ -2270,7 +2280,11 @@ static const struct sys_reg_desc sys_reg_descs[] = {
AA32_ID_SANITISED(ID_ISAR3_EL1),
AA32_ID_SANITISED(ID_ISAR4_EL1),
AA32_ID_SANITISED(ID_ISAR5_EL1),
- AA32_ID_SANITISED(ID_MMFR4_EL1),
+ AA32_ID_WRITABLE(ID_MMFR4_EL1, ID_MMFR4_EL1_LSM |
+ ID_MMFR4_EL1_HPDS |
+ ID_MMFR4_EL1_CnP |
+ ID_MMFR4_EL1_XNX |
+ ID_MMFR4_EL1_AC2),
AA32_ID_SANITISED(ID_ISAR6_EL1),
/* CRm=3 */
--
2.30.2
next reply other threads:[~2024-05-01 17:07 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-01 17:06 Russell King (Oracle) [this message]
2024-05-01 17:57 ` [PATCH RFC] KVM: arm64: allow ID_MMFR4_EL1 to be writable Oliver Upton
2024-05-01 18:08 ` Russell King (Oracle)
2024-05-01 18:59 ` Oliver Upton
2024-05-01 19:51 ` Russell King (Oracle)
2024-05-02 10:50 ` Russell King (Oracle)
2024-05-02 15:23 ` Marc Zyngier
2024-05-07 9:27 ` Russell King (Oracle)
2024-05-02 14:40 ` Russell King (Oracle)
2024-05-02 16:45 ` Oliver Upton
2024-05-08 12:06 ` Cornelia Huck
2024-05-08 17:14 ` Oliver Upton
2024-05-10 15:11 ` Cornelia Huck
2024-05-13 21:26 ` Oliver Upton
2024-05-22 10:14 ` Cornelia Huck
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