From: Will Deacon <will@kernel.org>
To: James Morse <james.morse@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Jing Zhang <jingzhangos@google.com>
Subject: Re: [PATCH v3 2/6] arm64: cpufeature: discover CPU support for MPAM
Date: Fri, 12 Apr 2024 15:41:20 +0100 [thread overview]
Message-ID: <20240412144119.GB28052@willie-the-truck> (raw)
In-Reply-To: <20240321165728.31907-3-james.morse@arm.com>
Hi James,
On Thu, Mar 21, 2024 at 04:57:24PM +0000, James Morse wrote:
> ARMv8.4 adds support for 'Memory Partitioning And Monitoring' (MPAM)
> which describes an interface to cache and bandwidth controls wherever
> they appear in the system.
>
> Add support to detect MPAM. Like SVE, MPAM has an extra id register that
> describes some more properties, including the virtualisation support,
> which is optional. Detect this separately so we can detect
> mismatched/insane systems, but still use MPAM on the host even if the
> virtualisation support is missing.
>
> MPAM needs enabling at the highest implemented exception level, otherwise
> the register accesses trap. The 'enabled' flag is accessible to lower
> exception levels, but its in a register that traps when MPAM isn't enabled.
> The cpufeature 'matches' hook is extended to test this on one of the
> CPUs, so that firmware can emulate MPAM as disabled if it is reserved
> for use by secure world.
>
> Secondary CPUs that appear late could trip cpufeature's 'lower safe'
> behaviour after the MPAM properties have been advertised to user-space.
> Add a verify call to ensure late secondaries match the existing CPUs.
>
> (If you have a boot failure that bisects here its likely your CPUs
> advertise MPAM in the id registers, but firmware failed to either enable
> or MPAM, or emulate the trap as if it were disabled)
I'm probably reading this wrong, but I'm a bit confused about the mixture
of open-coded system register definitions and updates to the 'sysreg'
file. For example:
> +/* CPU Registers */
> +#define MPAM_SYSREG_EN BIT_ULL(63)
> +#define MPAM_SYSREG_TRAP_IDR BIT_ULL(58)
> +#define MPAM_SYSREG_TRAP_MPAM0_EL1 BIT_ULL(49)
> +#define MPAM_SYSREG_TRAP_MPAM1_EL1 BIT_ULL(48)
> +#define MPAM_SYSREG_PMG_D GENMASK(47, 40)
> +#define MPAM_SYSREG_PMG_I GENMASK(39, 32)
> +#define MPAM_SYSREG_PARTID_D GENMASK(31, 16)
> +#define MPAM_SYSREG_PARTID_I GENMASK(15, 0)
MPAM_SYSREG_EN is then used in conjuntion with SYS_MPAM1_EL1:
> +static bool __maybe_unused
> +test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope)
> +{
> + if (!has_cpuid_feature(entry, scope))
> + return false;
> +
> + /* Check firmware actually enabled MPAM on this cpu. */
> + return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM_SYSREG_EN);
> +}
But that register has a 'sysreg' entry:
> +Sysreg MPAM1_EL1 3 0 10 5 0
> +Res0 63:48
> +Field 47:40 PMG_D
> +Field 39:32 PMG_I
> +Field 31:16 PARTID_D
> +Field 15:0 PARTID_I
> +EndSysreg
where bit 63 is RES0.
Will
next prev parent reply other threads:[~2024-04-12 14:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-21 16:57 [PATCH v3 0/6] KVM: arm64: Hide unsupported MPAM from the guest James Morse
2024-03-21 16:57 ` [PATCH v3 1/6] arm64: head.S: Initialise MPAM EL2 registers and disable traps James Morse
2024-03-21 16:57 ` [PATCH v3 2/6] arm64: cpufeature: discover CPU support for MPAM James Morse
2024-04-12 14:41 ` Will Deacon [this message]
2024-03-21 16:57 ` [PATCH v3 3/6] KVM: arm64: Fix missing traps of guest accesses to the MPAM registers James Morse
2024-03-21 16:57 ` [PATCH v3 4/6] KVM: arm64: Disable MPAM visibility by default and ignore VMM writes James Morse
2024-03-21 16:57 ` [PATCH v3 5/6] KVM: arm64: selftests: Move the bulky macro invocation to a helper James Morse
2024-03-21 16:57 ` [PATCH v3 6/6] KVM: arm64: selftests: Test ID_AA64PFR0.MPAM isn't completely ignored James Morse
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