From: Ramesh Thomas <ramesh.thomas@intel.com>
To: Gerd Bayer <gbayer@linux.ibm.com>,
Alex Williamson <alex.williamson@redhat.com>,
Jason Gunthorpe <jgg@ziepe.ca>,
Niklas Schnelle <schnelle@linux.ibm.com>
Cc: <kvm@vger.kernel.org>, <linux-s390@vger.kernel.org>,
Ankit Agrawal <ankita@nvidia.com>,
Yishai Hadas <yishaih@nvidia.com>,
Halil Pasic <pasic@linux.ibm.com>,
Julian Ruess <julianr@linux.ibm.com>,
Ben Segal <bpsegal@us.ibm.com>,
"Thomas, Ramesh" <ramesh.thomas@intel.com>
Subject: Re: [PATCH v3 2/3] vfio/pci: Support 8-byte PCI loads and stores
Date: Fri, 17 May 2024 03:29:55 -0700 [thread overview]
Message-ID: <d29a8b0d-37e6-4d87-9993-f195a5b7666c@intel.com> (raw)
In-Reply-To: <20240425165604.899447-3-gbayer@linux.ibm.com>
On 4/25/2024 9:56 AM, Gerd Bayer wrote:
> From: Ben Segal <bpsegal@us.ibm.com>
>
> Many PCI adapters can benefit or even require full 64bit read
> and write access to their registers. In order to enable work on
> user-space drivers for these devices add two new variations
> vfio_pci_core_io{read|write}64 of the existing access methods
> when the architecture supports 64-bit ioreads and iowrites.
This is indeed necessary as back to back 32 bit may not be optimal in
some devices.
>
> Signed-off-by: Ben Segal <bpsegal@us.ibm.com>
> Co-developed-by: Gerd Bayer <gbayer@linux.ibm.com>
> Signed-off-by: Gerd Bayer <gbayer@linux.ibm.com>
> ---
> drivers/vfio/pci/vfio_pci_rdwr.c | 16 ++++++++++++++++
> include/linux/vfio_pci_core.h | 3 +++
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c
> index 3335f1b868b1..8ed06edaee23 100644
> --- a/drivers/vfio/pci/vfio_pci_rdwr.c
> +++ b/drivers/vfio/pci/vfio_pci_rdwr.c
> @@ -89,6 +89,9 @@ EXPORT_SYMBOL_GPL(vfio_pci_core_ioread##size);
> VFIO_IOREAD(8)
> VFIO_IOREAD(16)
> VFIO_IOREAD(32)
> +#ifdef ioread64
> +VFIO_IOREAD(64)
> +#endif
>
> #define VFIO_IORDWR(size) \
> static int vfio_pci_core_iordwr##size(struct vfio_pci_core_device *vdev,\
> @@ -124,6 +127,10 @@ static int vfio_pci_core_iordwr##size(struct vfio_pci_core_device *vdev,\
> VFIO_IORDWR(8)
> VFIO_IORDWR(16)
> VFIO_IORDWR(32)
> +#if defined(ioread64) && defined(iowrite64)
> +VFIO_IORDWR(64)
> +#endif
> +
> /*
> * Read or write from an __iomem region (MMIO or I/O port) with an excluded
> * range which is inaccessible. The excluded range drops writes and fills
> @@ -148,6 +155,15 @@ ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem,
> else
> fillable = 0;
>
> +#if defined(ioread64) && defined(iowrite64)
Can we check for #ifdef CONFIG_64BIT instead? In x86, ioread64 and
iowrite64 get declared as extern functions if CONFIG_GENERIC_IOMAP is
defined and this check always fails. In include/asm-generic/io.h,
asm-generic/iomap.h gets included which declares them as extern functions.
One more thing to consider io-64-nonatomic-hi-lo.h and
io-64-nonatomic-lo-hi.h, if included would define it as a macro that
calls a function that rw 32 bits back to back.
> + if (fillable >= 8 && !(off % 8)) {
> + ret = vfio_pci_core_iordwr64(vdev, iswrite, test_mem,
> + io, buf, off, &filled);
> + if (ret)
> + return ret;
> +
> + } else
> +#endif /* defined(ioread64) && defined(iowrite64) */
> if (fillable >= 4 && !(off % 4)) {
> ret = vfio_pci_core_iordwr32(vdev, iswrite, test_mem,
> io, buf, off, &filled);
> diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h
> index a2c8b8bba711..f4cf5fd2350c 100644
> --- a/include/linux/vfio_pci_core.h
> +++ b/include/linux/vfio_pci_core.h
> @@ -157,5 +157,8 @@ int vfio_pci_core_ioread##size(struct vfio_pci_core_device *vdev, \
> VFIO_IOREAD_DECLATION(8)
> VFIO_IOREAD_DECLATION(16)
> VFIO_IOREAD_DECLATION(32)
> +#ifdef ioread64
> +VFIO_IOREAD_DECLATION(64)
nit: This macro is referenced only in this file. Can the typo be
corrected (_DECLARATION)?
> +#endif
>
> #endif /* VFIO_PCI_CORE_H */
next prev parent reply other threads:[~2024-05-17 10:30 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-25 16:56 [PATCH v3 0/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
2024-04-25 16:56 ` [PATCH v3 1/3] vfio/pci: Extract duplicated code into macro Gerd Bayer
2024-04-29 16:31 ` Alex Williamson
2024-05-17 14:22 ` Gerd Bayer
2024-04-29 20:09 ` Jason Gunthorpe
2024-04-29 22:11 ` Alex Williamson
2024-04-29 22:33 ` Jason Gunthorpe
2024-05-21 15:47 ` Gerd Bayer
2024-04-30 8:16 ` liulongfang
2024-05-17 10:47 ` Ramesh Thomas
2024-04-25 16:56 ` [PATCH v3 2/3] vfio/pci: Support 8-byte PCI loads and stores Gerd Bayer
2024-04-29 16:31 ` Alex Williamson
2024-05-21 15:50 ` Gerd Bayer
2024-05-17 10:29 ` Ramesh Thomas [this message]
2024-05-20 9:02 ` Tian, Kevin
2024-05-23 0:11 ` Ramesh Thomas
2024-05-23 21:52 ` Ramesh Thomas
2024-05-21 16:40 ` Gerd Bayer
2024-05-22 13:48 ` Jason Gunthorpe
2024-05-22 23:57 ` Ramesh Thomas
2024-04-25 16:56 ` [PATCH v3 3/3] vfio/pci: Continue to refactor vfio_pci_core_do_io_rw Gerd Bayer
2024-04-28 6:59 ` Tian, Kevin
2024-04-29 16:32 ` Alex Williamson
2024-05-21 16:43 ` Gerd Bayer
2024-05-17 11:41 ` Ramesh Thomas
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