From: isaku.yamahata@intel.com
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com,
Paolo Bonzini <pbonzini@redhat.com>,
erdemaktas@google.com, Sean Christopherson <seanjc@google.com>,
Sagi Shahar <sagis@google.com>,
David Matlack <dmatlack@google.com>,
Bagas Sanjaya <bagasdotme@gmail.com>
Subject: [PATCH v10 107/108] KVM: x86: design documentation on TDX support of x86 KVM TDP MMU
Date: Sat, 29 Oct 2022 23:23:48 -0700 [thread overview]
Message-ID: <91062ba1b723d5b866b17447e3f8f8addaa334ee.1667110240.git.isaku.yamahata@intel.com> (raw)
In-Reply-To: <cover.1667110240.git.isaku.yamahata@intel.com>
From: Isaku Yamahata <isaku.yamahata@intel.com>
Add a high level design document on TDX changes to TDP MMU.
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Co-developed-by: Bagas Sanjaya <bagasdotme@gmail.com>
Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com>
---
Documentation/virt/kvm/tdx-tdp-mmu.rst | 417 +++++++++++++++++++++++++
1 file changed, 417 insertions(+)
create mode 100644 Documentation/virt/kvm/tdx-tdp-mmu.rst
diff --git a/Documentation/virt/kvm/tdx-tdp-mmu.rst b/Documentation/virt/kvm/tdx-tdp-mmu.rst
new file mode 100644
index 000000000000..2d91c94e6d8f
--- /dev/null
+++ b/Documentation/virt/kvm/tdx-tdp-mmu.rst
@@ -0,0 +1,417 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Design of TDP MMU for TDX support
+=================================
+This document describes a (high level) design for TDX support of KVM TDP MMU of
+x86 KVM.
+
+In this document, we use "TD" or "guest TD" to differentiate it from the current
+"VM" (Virtual Machine), which is supported by KVM today.
+
+
+Background of TDX
+=================
+TD private memory is designed to hold TD private content, encrypted by the CPU
+using the TD ephemeral key. An encryption engine holds a table of encryption
+keys, and an encryption key is selected for each memory transaction based on a
+Host Key Identifier (HKID). By design, the host VMM does not have access to the
+encryption keys.
+
+In the first generation of MKTME, HKID is "stolen" from the physical address by
+allocating a configurable number of bits from the top of the physical address.
+The HKID space is partitioned into shared HKIDs for legacy MKTME accesses and
+private HKIDs for SEAM-mode-only accesses. We use 0 for the shared HKID on the
+host so that MKTME can be opaque or bypassed on the host.
+
+During TDX non-root operation (i.e. guest TD), memory accesses can be qualified
+as either shared or private, based on the value of a new SHARED bit in the Guest
+Physical Address (GPA). The CPU translates shared GPAs using the usual VMX EPT
+(Extended Page Table) or "Shared EPT" (in this document), which resides in the
+host VMM memory. The Shared EPT is directly managed by the host VMM - the same
+as with the current VMX. Since guest TDs usually require I/O, and the data
+exchange needs to be done via shared memory, thus KVM needs to use the current
+EPT functionality even for TDs.
+
+The CPU translates private GPAs using a separate Secure EPT. The Secure EPT
+pages are encrypted and integrity-protected with the TD's ephemeral private key.
+Secure EPT can be managed _indirectly_ by the host VMM, using the TDX interface
+functions (SEAMCALLs), and thus conceptually Secure EPT is a subset of EPT
+because not all functionalities are available.
+
+Since the execution of such interface functions takes much longer time than
+accessing memory directly, in KVM we use the existing TDP code to mirror the
+Secure EPT for the TD. And we think there are at least two options today in
+terms of the timing for executing such SEAMCALLs:
+
+1. synchronous, i.e. while walking the TDP page tables, or
+2. post-walk, i.e. record what needs to be done to the real Secure EPT during
+ the walk, and execute SEAMCALLs later.
+
+The option 1 seems to be more intuitive and simpler, but the Secure EPT
+concurrency rules are different from the ones of the TDP or EPT. For example,
+MEM.SEPT.RD acquire shared access to the whole Secure EPT tree of the target
+
+Secure EPT(SEPT) operations
+---------------------------
+Secure EPT is an Extended Page Table for GPA-to-HPA translation of TD private
+HPA. A Secure EPT is designed to be encrypted with the TD's ephemeral private
+key. SEPT pages are allocated by the host VMM via Intel TDX functions, but their
+content is intended to be hidden and is not architectural.
+
+Unlike the conventional EPT, the CPU can't directly read/write its entry.
+Instead, TDX SEAMCALL API is used. Several SEAMCALLs correspond to operation on
+the EPT entry.
+
+* TDH.MEM.SEPT.ADD():
+
+ Add a secure EPT page from the secure EPT tree. This corresponds to updating
+ the non-leaf EPT entry with present bit set
+
+* TDH.MEM.SEPT.REMOVE():
+
+ Remove the secure page from the secure EPT tree. There is no corresponding
+ to the EPT operation.
+
+* TDH.MEM.SEPT.RD():
+
+ Read the secure EPT entry. This corresponds to reading the EPT entry as
+ memory. Please note that this is much slower than direct memory reading.
+
+* TDH.MEM.PAGE.ADD() and TDH.MEM.PAGE.AUG():
+
+ Add a private page to the secure EPT tree. This corresponds to updating the
+ leaf EPT entry with present bit set.
+
+* THD.MEM.PAGE.REMOVE():
+
+ Remove a private page from the secure EPT tree. There is no corresponding
+ to the EPT operation.
+
+* TDH.MEM.RANGE.BLOCK():
+
+ This (mostly) corresponds to clearing the present bit of the leaf EPT entry.
+ Note that the private page is still linked in the secure EPT. To remove it
+ from the secure EPT, TDH.MEM.SEPT.REMOVE() and TDH.MEM.PAGE.REMOVE() needs to
+ be called.
+
+* TDH.MEM.TRACK():
+
+ Increment the TLB epoch counter. This (mostly) corresponds to EPT TLB flush.
+ Note that the private page is still linked in the secure EPT. To remove it
+ from the secure EPT, tdh_mem_page_remove() needs to be called.
+
+
+Adding private page
+-------------------
+The procedure of populating the private page looks as follows.
+
+1. TDH.MEM.SEPT.ADD(512G level)
+2. TDH.MEM.SEPT.ADD(1G level)
+3. TDH.MEM.SEPT.ADD(2M level)
+4. TDH.MEM.PAGE.AUG(4K level)
+
+Those operations correspond to updating the EPT entries.
+
+Dropping private page and TLB shootdown
+---------------------------------------
+The procedure of dropping the private page looks as follows.
+
+1. TDH.MEM.RANGE.BLOCK(4K level)
+
+ This mostly corresponds to clear the present bit in the EPT entry. This
+ prevents (or blocks) TLB entry from creating in the future. Note that the
+ private page is still linked in the secure EPT tree and the existing cache
+ entry in the TLB isn't flushed.
+
+2. TDH.MEM.TRACK(range) and TLB shootdown
+
+ This mostly corresponds to the EPT TLB shootdown. Because all vcpus share
+ the same Secure EPT, all vcpus need to flush TLB.
+
+ * TDH.MEM.TRACK(range) by one vcpu. It increments the global internal TLB
+ epoch counter.
+
+ * send IPI to remote vcpus
+ * Other vcpu exits to VMM from guest TD and then re-enter. TDH.VP.ENTER().
+ * TDH.VP.ENTER() checks the TLB epoch counter and If its TLB is old, flush
+ TLB.
+
+ Note that only single vcpu issues tdh_mem_track().
+
+ Note that the private page is still linked in the secure EPT tree, unlike the
+ conventional EPT.
+
+3. TDH.MEM.PAGE.PROMOTE, TDH.MEM.PAGEDEMOTE(), TDH.MEM.PAGE.RELOCATE(), or
+ TDH.MEM.PAGE.REMOVE()
+
+ There is no corresponding operation to the conventional EPT.
+
+ * When changing page size (e.g. 4K <-> 2M) TDH.MEM.PAGE.PROMOTE() or
+ TDH.MEM.PAGE.DEMOTE() is used. During those operation, the guest page is
+ kept referenced in the Secure EPT.
+
+ * When migrating page, TDH.MEM.PAGE.RELOCATE(). This requires both source
+ page and destination page.
+ * when destroying TD, TDH.MEM.PAGE.REMOVE() removes the private page from the
+ secure EPT tree. In this case TLB shootdown is not needed because vcpus
+ don't run any more.
+
+The basic idea for TDX support
+==============================
+Because shared EPT is the same as the existing EPT, use the existing logic for
+shared EPT. On the other hand, secure EPT requires additional operations
+instead of directly reading/writing of the EPT entry.
+
+On EPT violation, The KVM mmu walks down the EPT tree from the root, determines
+the EPT entry to operate, and updates the entry. If necessary, a TLB shootdown
+is done. Because it's very slow to directly walk secure EPT by TDX SEAMCALL,
+TDH.MEM.SEPT.RD(), the mirror of secure EPT is created and maintained. Add
+hooks to KVM MMU to reuse the existing code.
+
+EPT violation on shared GPA
+---------------------------
+(1) EPT violation on shared GPA or zapping shared GPA
+ ::
+
+ walk down shared EPT tree (the existing code)
+ |
+ |
+ V
+ shared EPT tree (CPU refers.)
+
+(2) update the EPT entry. (the existing code)
+
+ TLB shootdown in the case of zapping.
+
+
+EPT violation on private GPA
+----------------------------
+(1) EPT violation on private GPA or zapping private GPA
+ ::
+
+ walk down the mirror of secure EPT tree (mostly same as the existing code)
+ |
+ |
+ V
+ mirror of secure EPT tree (KVM MMU software only. reuse of the existing code)
+
+(2) update the (mirrored) EPT entry. (mostly same as the existing code)
+
+(3) call the hooks with what EPT entry is changed
+ ::
+
+ |
+ NEW: hooks in KVM MMU
+ |
+ V
+ secure EPT root(CPU refers)
+
+(4) the TDX backend calls necessary TDX SEAMCALLs to update real secure EPT.
+
+The major modification is to add hooks for the TDX backend for additional
+operations and to pass down which EPT, shared EPT, or private EPT is used, and
+twist the behavior if we're operating on private EPT.
+
+The following depicts the relationship.
+::
+
+ KVM | TDX module
+ | | |
+ -------------+---------- | |
+ | | | |
+ V V | |
+ shared GPA private GPA | |
+ CPU shared EPT pointer KVM private EPT pointer | CPU secure EPT pointer
+ | | | |
+ | | | |
+ V V | V
+ shared EPT private EPT<-------mirror----->Secure EPT
+ | | | |
+ | \--------------------+------\ |
+ | | | |
+ V | V V
+ shared guest page | private guest page
+ |
+ |
+ non-encrypted memory | encrypted memory
+ |
+
+shared EPT: CPU and KVM walk with shared GPA
+ Maintained by the existing code
+private EPT: KVM walks with private GPA
+ Maintained by the twisted existing code
+secure EPT: CPU walks with private GPA.
+ Maintained by TDX module with TDX SEAMCALLs via hooks
+
+
+Tracking private EPT page
+=========================
+Shared EPT pages are managed by struct kvm_mmu_page. They are linked in a list
+structure. When necessary, the list is traversed to operate on. Private EPT
+pages have different characteristics. For example, private pages can't be
+swapped out. When shrinking memory, we'd like to traverse only shared EPT pages
+and skip private EPT pages. Likewise, page migration isn't supported for
+private pages (yet). Introduce an additional list to track shared EPT pages and
+track private EPT pages independently.
+
+At the beginning of EPT violation, the fault handler knows fault GPA, thus it
+knows which EPT to operate on, private or shared. If it's private EPT,
+an additional task is done. Something like "if (private) { callback a hook }".
+Since the fault handler has deep function calls, it's cumbersome to hold the
+information of which EPT is operating. Options to mitigate it are
+
+1. Pass the information as an argument for the function call.
+2. Record the information in struct kvm_mmu_page somehow.
+3. Record the information in vcpu structure.
+
+Option 2 was chosen. Because option 1 requires modifying all the functions. It
+would affect badly to the normal case. Option 3 doesn't work well because in
+some cases, we need to walk both private and shared EPT.
+
+The role of the EPT page can be utilized and one bit can be curved out from
+unused bits in struct kvm_mmu_page_role. When allocating the EPT page,
+initialize the information. Mostly struct kvm_mmu_page is available because
+we're operating on EPT pages.
+
+
+The conversion of private GPA and shared GPA
+============================================
+A page of a given GPA can be assigned to only private GPA xor shared GPA at one
+time. The GPA can't be accessed simultaneously via both private GPA and shared
+GPA. On guest startup, all the GPAs are assigned as private. Guest converts
+the range of GPA to shared (or private) from private (or shared) by MapGPA
+hypercall. MapGPA hypercall takes the start GPA and the size of the region. If
+the given start GPA is shared, VMM converts the region into shared (if it's
+already shared, nop). If the start GPA is private, VMM converts the region into
+private. It implies the guest won't access the unmapped region. private(or
+shared) region after converting to shared(or private).
+
+If the guest TD triggers an EPT violation on the already converted region, the
+access won't be allowed (loop in EPT violation) until other vcpu converts back
+the region.
+
+KVM MMU records which GPA is allowed to access, private or shared by xarray.
+
+
+The original TDP MMU and race condition
+=======================================
+Because vcpus share the EPT, once the EPT entry is zapped, we need to shootdown
+TLB. Send IPI to remote vcpus. Remote vcpus flush their down TLBs. Until TLB
+shootdown is done, vcpus may reference the zapped guest page.
+
+TDP MMU uses read lock of mmu_lock to mitigate vcpu contention. When read lock
+is obtained, it depends on the atomic update of the EPT entry. (On the other
+hand legacy MMU uses write lock.) When vcpu is populating/zapping the EPT entry
+with a read lock held, other vcpu may be populating or zapping the same EPT
+entry at the same time.
+
+To avoid the race condition, the entry is frozen. It means the EPT entry is set
+to the special value, REMOVED_SPTE which clears the present bit. And then after
+TLB shootdown, update the EPT entry to the final value.
+
+Concurrent zapping
+------------------
+1. read lock
+2. freeze the EPT entry (atomically set the value to REMOVED_SPTE)
+ If other vcpu froze the entry, restart page fault.
+3. TLB shootdown
+
+ * send IPI to remote vcpus
+ * TLB flush (local and remote)
+
+ For each entry update, TLB shootdown is needed because of the
+ concurrency.
+4. atomically set the EPT entry to the final value
+5. read unlock
+
+Concurrent populating
+---------------------
+In the case of populating the non-present EPT entry, atomically update the EPT
+entry.
+
+1. read lock
+
+2. atomically update the EPT entry
+ If other vcpu frozen the entry or updated the entry, restart page fault.
+
+3. read unlock
+
+In the case of updating the present EPT entry (e.g. page migration), the
+operation is split into two. Zapping the entry and populating the entry.
+
+1. read lock
+2. zap the EPT entry. follow the concurrent zapping case.
+3. populate the non-present EPT entry.
+4. read unlock
+
+Non-concurrent batched zapping
+------------------------------
+In some cases, zapping the ranges is done exclusively with a write lock held.
+In this case, the TLB shootdown is batched into one.
+
+1. write lock
+2. zap the EPT entries by traversing them
+3. TLB shootdown
+4. write unlock
+
+For Secure EPT, TDX SEAMCALLs are needed in addition to updating the mirrored
+EPT entry.
+
+TDX concurrent zapping
+----------------------
+Add a hook for TDX SEAMCALLs at the step of the TLB shootdown.
+
+1. read lock
+2. freeze the EPT entry(set the value to REMOVED_SPTE)
+3. TLB shootdown via a hook
+
+ * TLB.MEM.RANGE.BLOCK()
+ * TLB.MEM.TRACK()
+ * send IPI to remote vcpus
+
+4. set the EPT entry to the final value
+5. read unlock
+
+TDX concurrent populating
+-------------------------
+TDX SEAMCALLs are required in addition to operating the mirrored EPT entry. The
+frozen entry is utilized by following the zapping case to avoid the race
+condition. A hook can be added.
+
+1. read lock
+2. freeze the EPT entry
+3. hook
+
+ * TDH_MEM_SEPT_ADD() for non-leaf or TDH_MEM_PAGE_AUG() for leaf.
+
+4. set the EPT entry to the final value
+5. read unlock
+
+Without freezing the entry, the following race can happen. Suppose two vcpus
+are faulting on the same GPA and the 2M and 4K level entries aren't populated
+yet.
+
+* vcpu 1: update 2M level EPT entry
+* vcpu 2: update 4K level EPT entry
+* vcpu 2: TDX SEAMCALL to update 4K secure EPT entry => error
+* vcpu 1: TDX SEAMCALL to update 2M secure EPT entry
+
+
+TDX non-concurrent batched zapping
+----------------------------------
+For simplicity, the procedure of concurrent populating is utilized. The
+procedure can be optimized later.
+
+
+Co-existing with unmapping guest private memory
+===============================================
+TODO. This needs to be addressed.
+
+
+Restrictions or future work
+===========================
+The following features aren't supported yet at the moment.
+
+* optimizing non-concurrent zap
+* Large page
+* Page migration
--
2.25.1
next prev parent reply other threads:[~2022-10-30 6:31 UTC|newest]
Thread overview: 228+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-30 6:22 [PATCH v10 000/108] KVM TDX basic feature support isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 001/108] KVM: VMX: Move out vmx_x86_ops to 'main.c' to wrap VMX and TDX isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 002/108] KVM: x86: Refactor KVM VMX module init/exit functions isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 003/108] KVM: TDX: Add placeholders for TDX VM/vcpu structure isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 004/108] x86/virt/tdx: Add a helper function to return system wide info about TDX module isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 005/108] KVM: TDX: Initialize the TDX module when loading the KVM intel kernel module isaku.yamahata
2022-11-08 1:29 ` Huang, Kai
2022-11-08 18:48 ` Sean Christopherson
2022-11-14 23:18 ` Isaku Yamahata
2022-11-15 1:58 ` Huang, Kai
2022-11-15 12:22 ` Erdem Aktas
2022-11-17 17:33 ` Isaku Yamahata
2023-01-11 22:02 ` Erdem Aktas
2023-01-12 3:08 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 006/108] KVM: x86: Introduce vm_type to differentiate default VMs from confidential VMs isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 007/108] KVM: TDX: Make TDX VM type supported isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 008/108] [MARKER] The start of TDX KVM patch series: TDX architectural definitions isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 009/108] KVM: TDX: Define " isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 010/108] KVM: TDX: Add TDX "architectural" error codes isaku.yamahata
2022-10-31 9:22 ` Binbin Wu
2022-11-03 0:05 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 011/108] KVM: TDX: Add C wrapper functions for SEAMCALLs to the TDX module isaku.yamahata
2022-11-23 10:00 ` Zhi Wang
2022-12-15 19:45 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 012/108] KVM: TDX: Add helper functions to print TDX SEAMCALL error isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 013/108] [MARKER] The start of TDX KVM patch series: TD VM creation/destruction isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 014/108] KVM: TDX: Stub in tdx.h with structs, accessors, and VMCS helpers isaku.yamahata
2022-10-31 11:39 ` Binbin Wu
2022-11-03 0:57 ` Isaku Yamahata
2022-11-10 11:11 ` Huang, Kai
2022-10-30 6:22 ` [PATCH v10 015/108] x86/cpu: Add helper functions to allocate/free TDX private host key id isaku.yamahata
2022-11-08 9:16 ` Huang, Kai
2022-11-17 17:34 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 016/108] KVM: TDX: create/destroy VM structure isaku.yamahata
2022-11-10 11:04 ` Huang, Kai
2022-11-17 17:45 ` Isaku Yamahata
2022-11-15 0:06 ` Sagi Shahar
2022-11-17 17:48 ` Isaku Yamahata
2022-11-17 23:45 ` Sagi Shahar
2022-11-23 10:36 ` Zhi Wang
2022-12-15 19:59 ` Isaku Yamahata
2022-12-09 19:15 ` Ackerley Tng
2022-12-15 20:59 ` Isaku Yamahata
2023-01-03 18:17 ` Ackerley Tng
2023-01-04 3:58 ` Wang, Lei
2022-10-30 6:22 ` [PATCH v10 017/108] KVM: TDX: Refuse to unplug the last cpu on the package isaku.yamahata
2022-11-02 8:06 ` Binbin Wu
2022-11-03 2:01 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 018/108] KVM: TDX: x86: Add ioctl to get TDX systemwide parameters isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 019/108] KVM: TDX: Add place holder for TDX VM specific mem_enc_op ioctl isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 020/108] KVM: Support KVM_CAP_MAX_VCPUS for KVM_ENABLE_CAP isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 021/108] KVM: TDX: initialize VM with TDX specific parameters isaku.yamahata
2022-11-16 5:34 ` Wang, Lei
2022-11-17 17:51 ` Isaku Yamahata
2023-01-04 7:59 ` Wang, Lei
2023-01-12 3:12 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 022/108] KVM: TDX: Make pmu_intel.c ignore guest TD case isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 023/108] [MARKER] The start of TDX KVM patch series: TD vcpu creation/destruction isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 024/108] KVM: TDX: allocate/free TDX vcpu structure isaku.yamahata
2022-11-14 6:46 ` Yuan Yao
2022-12-15 21:28 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 025/108] KVM: TDX: Do TDX specific vcpu initialization isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 026/108] KVM: TDX: Use private memory for TDX isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 027/108] [MARKER] The start of TDX KVM patch series: KVM MMU GPA shared bits isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 028/108] KVM: x86/mmu: introduce config for PRIVATE KVM MMU isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 029/108] KVM: x86/mmu: Add address conversion functions for TDX shared bit of GPA isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 030/108] [MARKER] The start of TDX KVM patch series: KVM TDP refactoring for TDX isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 031/108] KVM: x86/mmu: Replace hardcoded value 0 for the initial value for SPTE isaku.yamahata
2022-11-03 7:17 ` Binbin Wu
2022-11-03 8:00 ` Binbin Wu
2022-11-08 11:33 ` Huang, Kai
2022-11-17 17:55 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 032/108] KVM: x86/mmu: Make sync_page not use hard-coded 0 as the initial SPTE value isaku.yamahata
2022-11-09 11:24 ` Huang, Kai
2022-11-17 17:55 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 033/108] KVM: x86/mmu: Allow non-zero value for non-present SPTE and removed SPTE isaku.yamahata
2022-11-09 11:24 ` Huang, Kai
2022-11-17 17:58 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 034/108] KVM: x86/mmu: Add Suppress VE bit to shadow_mmio_{value, mask} isaku.yamahata
2022-11-09 11:48 ` Huang, Kai
2022-11-17 18:02 ` Isaku Yamahata
2022-11-28 23:51 ` Sean Christopherson
2022-10-30 6:22 ` [PATCH v10 035/108] KVM: x86/mmu: Track shadow MMIO value on a per-VM basis isaku.yamahata
2022-11-09 12:27 ` Huang, Kai
2022-11-22 2:10 ` Yan Zhao
2022-11-25 0:13 ` Huang, Kai
2022-11-25 0:12 ` Yan Zhao
2022-11-25 0:45 ` Huang, Kai
2022-11-25 0:37 ` Yan Zhao
2022-11-25 1:07 ` Huang, Kai
2022-11-25 1:04 ` Yan Zhao
2022-11-28 23:49 ` Sean Christopherson
2022-10-30 6:22 ` [PATCH v10 036/108] KVM: TDX: Enable mmio spte caching always for TDX isaku.yamahata
2022-11-09 12:46 ` Huang, Kai
2022-10-30 6:22 ` [PATCH v10 037/108] KVM: x86/mmu: Disallow fast page fault on private GPA isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 038/108] KVM: x86/mmu: Allow per-VM override of the TDP max page level isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 039/108] KVM: VMX: Introduce test mode related to EPT violation VE isaku.yamahata
2022-11-03 13:41 ` Binbin Wu
2022-11-03 20:13 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 040/108] [MARKER] The start of TDX KVM patch series: KVM TDP MMU hooks isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 041/108] KVM: x86/tdp_mmu: refactor kvm_tdp_mmu_map() isaku.yamahata
2022-11-16 9:42 ` Huang, Kai
2022-11-17 18:37 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 042/108] KVM: x86/tdp_mmu: Init role member of struct kvm_mmu_page at allocation isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 043/108] KVM: x86/mmu: Require TDP MMU for TDX isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 044/108] KVM: x86/mmu: Add a new is_private member for union kvm_mmu_page_role isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 045/108] KVM: x86/mmu: Add a private pointer to struct kvm_mmu_page isaku.yamahata
2022-11-16 10:32 ` Huang, Kai
2022-11-16 11:53 ` Huang, Kai
2022-11-17 19:25 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 046/108] KVM: Add flags to struct kvm_gfn_range isaku.yamahata
2022-12-14 10:51 ` Huang, Kai
2022-12-15 22:10 ` Isaku Yamahata
2022-12-15 22:41 ` Huang, Kai
2022-10-30 6:22 ` [PATCH v10 047/108] KVM: x86/tdp_mmu: Don't zap private pages for unsupported cases isaku.yamahata
2022-11-22 21:26 ` Ackerley Tng
2022-12-14 11:17 ` Huang, Kai
2022-12-15 22:46 ` Isaku Yamahata
2022-12-15 23:03 ` Huang, Kai
2022-12-15 23:27 ` Huang, Kai
2022-10-30 6:22 ` [PATCH v10 048/108] KVM: x86/tdp_mmu: Make handle_changed_spte() return value isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 049/108] KVM: x86/tdp_mmu: Support TDX private mapping for TDP MMU isaku.yamahata
2022-11-08 13:41 ` Binbin Wu
2022-11-17 19:59 ` Isaku Yamahata
2022-11-16 1:40 ` Chenyi Qiang
2022-11-17 19:26 ` Isaku Yamahata
2022-11-16 11:58 ` Huang, Kai
2022-11-17 19:31 ` Isaku Yamahata
2022-10-30 6:22 ` [PATCH v10 050/108] [MARKER] The start of TDX KVM patch series: TDX EPT violation isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 051/108] KVM: x86/mmu: Disallow dirty logging for x86 TDX isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 052/108] KVM: x86/tdp_mmu: Ignore unsupported mmu operation on private GFNs isaku.yamahata
2022-12-05 14:23 ` Wang, Wei W
2022-12-15 23:21 ` Isaku Yamahata
2022-12-19 13:15 ` Wang, Wei W
2022-10-30 6:22 ` [PATCH v10 053/108] KVM: VMX: Split out guts of EPT violation to common/exposed function isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 054/108] KVM: VMX: Move setting of EPT MMU masks to common VT-x code isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 055/108] KVM: TDX: Add load_mmu_pgd method for TDX isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 056/108] KVM: TDX: don't request KVM_REQ_APIC_PAGE_RELOAD isaku.yamahata
2022-11-21 23:55 ` Huang, Kai
2022-12-16 0:11 ` Isaku Yamahata
2022-12-16 0:31 ` Huang, Kai
2022-10-30 6:22 ` [PATCH v10 057/108] KVM: x86/VMX: introduce vmx tlb_remote_flush and tlb_remote_flush_with_range isaku.yamahata
2022-10-30 6:22 ` [PATCH v10 058/108] KVM: TDX: TDP MMU TDX support isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 059/108] [MARKER] The start of TDX KVM patch series: KVM TDP MMU MapGPA isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 060/108] KVM: Add functions to set GFN to private or shared isaku.yamahata
2022-11-01 10:21 ` Xiaoyao Li
2022-11-03 2:01 ` Isaku Yamahata
2022-11-09 13:18 ` Binbin Wu
2022-10-30 6:23 ` [PATCH v10 061/108] KVM: x86/mmu: Introduce kvm_mmu_map_tdp_page() for use by TDX isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 062/108] KVM: x86/tdp_mmu: implement MapGPA hypercall for TDX isaku.yamahata
2022-11-09 15:05 ` Binbin Wu
2022-12-09 0:01 ` Vishal Annapurve
2022-12-16 0:31 ` Isaku Yamahata
2022-12-16 0:18 ` Isaku Yamahata
2022-10-30 6:23 ` [PATCH v10 063/108] [MARKER] The start of TDX KVM patch series: TD finalization isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 064/108] KVM: TDX: Create initial guest memory isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 065/108] KVM: TDX: Finalize VM initialization isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 066/108] [MARKER] The start of TDX KVM patch series: TD vcpu enter/exit isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 067/108] KVM: TDX: Add helper assembly function to TDX vcpu isaku.yamahata
2023-01-17 23:36 ` Ackerley Tng
2022-10-30 6:23 ` [PATCH v10 068/108] KVM: TDX: Implement TDX vcpu enter/exit path isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 069/108] KVM: TDX: vcpu_run: save/restore host state(host kernel gs) isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 070/108] KVM: TDX: restore host xsave state when exit from the guest TD isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 071/108] KVM: x86: Allow to update cached values in kvm_user_return_msrs w/o wrmsr isaku.yamahata
2022-11-14 7:36 ` Binbin Wu
2022-11-17 20:10 ` Isaku Yamahata
2022-10-30 6:23 ` [PATCH v10 072/108] KVM: TDX: restore user ret MSRs isaku.yamahata
2022-11-14 7:49 ` Binbin Wu
2022-11-17 20:14 ` Isaku Yamahata
2022-10-30 6:23 ` [PATCH v10 073/108] [MARKER] The start of TDX KVM patch series: TD vcpu exits/interrupts/hypercalls isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 074/108] KVM: TDX: complete interrupts after tdexit isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 075/108] KVM: TDX: restore debug store when TD exit isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 076/108] KVM: TDX: handle vcpu migration over logical processor isaku.yamahata
2022-11-15 2:28 ` Binbin Wu
2022-11-17 20:24 ` Isaku Yamahata
2022-10-30 6:23 ` [PATCH v10 077/108] KVM: x86: Add a switch_db_regs flag to handle TDX's auto-switched behavior isaku.yamahata
2022-11-16 2:41 ` Binbin Wu
2022-12-16 1:12 ` Isaku Yamahata
2022-10-30 6:23 ` [PATCH v10 078/108] KVM: TDX: Add support for find pending IRQ in a protected local APIC isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 079/108] KVM: x86: Assume timer IRQ was injected if APIC state is proteced isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 080/108] KVM: TDX: remove use of struct vcpu_vmx from posted_interrupt.c isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 081/108] KVM: TDX: Implement interrupt injection isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 082/108] KVM: TDX: Implements vcpu request_immediate_exit isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 083/108] KVM: TDX: Implement methods to inject NMI isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 084/108] KVM: VMX: Modify NMI and INTR handlers to take intr_info as function argument isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 085/108] KVM: VMX: Move NMI/exception handler to common helper isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 086/108] KVM: x86: Split core of hypercall emulation to helper function isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 087/108] KVM: TDX: Add a place holder to handle TDX VM exit isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 088/108] KVM: TDX: Retry seamcall when TDX_OPERAND_BUSY with operand SEPT isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 089/108] KVM: TDX: handle EXIT_REASON_OTHER_SMI isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 090/108] KVM: TDX: handle ept violation/misconfig exit isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 091/108] KVM: TDX: handle EXCEPTION_NMI and EXTERNAL_INTERRUPT isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 092/108] KVM: TDX: Add a place holder for handler of TDX hypercalls (TDG.VP.VMCALL) isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 093/108] KVM: TDX: handle KVM hypercall with TDG.VP.VMCALL isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 094/108] KVM: TDX: Handle TDX PV CPUID hypercall isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 095/108] KVM: TDX: Handle TDX PV HLT hypercall isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 096/108] KVM: TDX: Handle TDX PV port io hypercall isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 097/108] KVM: TDX: Handle TDX PV MMIO hypercall isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 098/108] KVM: TDX: Implement callbacks for MSR operations for TDX isaku.yamahata
2022-11-23 14:25 ` Binbin Wu
2022-12-16 1:29 ` Isaku Yamahata
2022-12-14 11:22 ` Huang, Kai
2022-12-16 1:39 ` Isaku Yamahata
2023-01-04 21:20 ` Ackerley Tng
2023-01-12 10:06 ` Isaku Yamahata
2022-10-30 6:23 ` [PATCH v10 099/108] KVM: TDX: Handle TDX PV rdmsr/wrmsr hypercall isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 100/108] KVM: TDX: Handle TDX PV report fatal error hypercall isaku.yamahata
2022-11-23 14:47 ` Binbin Wu
2022-10-30 6:23 ` [PATCH v10 101/108] KVM: TDX: Handle TDX PV map_gpa hypercall isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 102/108] KVM: TDX: Handle TDG.VP.VMCALL<GetTdVmCallInfo> hypercall isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 103/108] KVM: TDX: Silently discard SMI request isaku.yamahata
2022-10-30 6:23 ` [PATCH v10 104/108] KVM: TDX: Silently ignore INIT/SIPI isaku.yamahata
2022-11-23 15:17 ` Binbin Wu
2022-12-16 3:50 ` Isaku Yamahata
2022-12-16 15:49 ` Sean Christopherson
2022-10-30 6:23 ` [PATCH v10 105/108] KVM: TDX: Add methods to ignore accesses to CPU state isaku.yamahata
2022-11-22 1:18 ` Huang, Kai
2022-12-14 11:43 ` Huang, Kai
2022-12-16 5:26 ` Isaku Yamahata
2022-12-19 10:46 ` Huang, Kai
2022-10-30 6:23 ` [PATCH v10 106/108] Documentation/virt/kvm: Document on Trust Domain Extensions(TDX) isaku.yamahata
2022-11-25 3:49 ` Binbin Wu
2022-12-16 3:58 ` Isaku Yamahata
2022-10-30 6:23 ` isaku.yamahata [this message]
2022-10-31 4:23 ` [PATCH v10 107/108] KVM: x86: design documentation on TDX support of x86 KVM TDP MMU Bagas Sanjaya
2022-10-30 6:23 ` [PATCH v10 108/108] [MARKER] the end of (the first phase of) TDX KVM patch series isaku.yamahata
2023-01-03 8:26 ` [PATCH v10 000/108] KVM TDX basic feature support Wang, Lei
2023-01-12 16:16 ` Isaku Yamahata
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