From: Mingwei Zhang <mizhang@google.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Xiong Zhang <xiong.y.zhang@intel.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Kan Liang <kan.liang@intel.com>,
Zhenyu Wang <zhenyuw@linux.intel.com>,
Manali Shukla <manali.shukla@amd.com>,
Sandipan Das <sandipan.das@amd.com>
Cc: Jim Mattson <jmattson@google.com>,
Stephane Eranian <eranian@google.com>,
Ian Rogers <irogers@google.com>,
Namhyung Kim <namhyung@kernel.org>,
Mingwei Zhang <mizhang@google.com>,
gce-passthrou-pmu-dev@google.com,
Samantha Alt <samantha.alt@intel.com>,
Zhiyuan Lv <zhiyuan.lv@intel.com>,
Yanfei Xu <yanfei.xu@intel.com>, maobibo <maobibo@loongson.cn>,
Like Xu <like.xu.linux@gmail.com>,
Peter Zijlstra <peterz@infradead.org>,
kvm@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: [PATCH v2 00/54] Mediated Passthrough vPMU 2.0 for x86
Date: Mon, 6 May 2024 05:29:25 +0000 [thread overview]
Message-ID: <20240506053020.3911940-1-mizhang@google.com> (raw)
In this version, we added the mediated passthrough vPMU support for AMD.
This is 1st version that comes up with a full x86 support on the vPMU
new design.
Major changes:
- AMD support integration. Supporting guest PerfMon v1 and v2.
- Ensure !exclude_guest events only exist prior to mediate passthrough
vPMU loaded. [sean]
- Update PMU MSR interception according to exposed counters and pmu
version. [mingwei reported pmu_counters_test fails]
- Enforce RDPMC interception unless all counters exposed to guest. This
removes a hack in RFCv1 where we pass through RDPMC and zero
unexposed counters. [jim/sean]
- Combine the PMU context switch for both AMD and Intel.
- Because of RDPMC interception, update PMU context switch code by
removing the "zeroing out" logic when restoring the guest context.
[jim/sean: intercept rdpmc]
Minor changes:
- Flip enable_passthrough_pmu to false and change to a vendor param.
- Remove "Intercept full-width GP counter MSRs by checking with perf
capabilities".
- Remove the write to pmc patch.
- Move host_perf_cap as an independent variable, will update after
https://lore.kernel.org/all/20240423221521.2923759-1-seanjc@google.com/
TODOs:
- Simplify enabling code for mediated passthrough vPMU.
- Further optimization on PMU context switch.
On-going discussions:
- Final name of mediated passthrough vPMU.
- PMU context switch optimizations.
Testing:
- Testcases:
- selftest: pmu_counters_test
- selftest: pmu_event_filter_test
- kvm-unit-tests: pmu
- qemu based ubuntu 20.04 (guest kernel: 5.10 and 6.7.9)
- Platforms:
- genoa
- skylake
- icelake
- sapphirerapids
- emeraldrapids
Ongoing Issues:
- AMD platform [milan]:
- ./pmu_event_filter_test error:
- test_amd_deny_list: Branch instructions retired = 44 (expected 42)
- test_without_filter: Branch instructions retired = 44 (expected 42)
- test_member_allow_list: Branch instructions retired = 44 (expected 42)
- test_not_member_deny_list: Branch instructions retired = 44 (expected 42)
- Intel platform [skylake]:
- kvm-unit-tests/pmu fails with two errors:
- FAIL: Intel: TSX cycles: gp cntr-3 with a value of 0
- FAIL: Intel: full-width writes: TSX cycles: gp cntr-3 with a value of 0
Installation guidance:
- echo 0 > /proc/sys/kernel/nmi_watchdog
- modprobe kvm_{amd,intel} enable_passthrough_pmu=Y 2>/dev/null
v1: https://lore.kernel.org/all/20240126085444.324918-1-xiong.y.zhang@linux.intel.com/
Dapeng Mi (3):
x86/msr: Introduce MSR_CORE_PERF_GLOBAL_STATUS_SET
KVM: x86/pmu: Introduce macro PMU_CAP_PERF_METRICS
KVM: x86/pmu: Add intel_passthrough_pmu_msrs() to pass-through PMU
MSRs
Kan Liang (3):
perf: Support get/put passthrough PMU interfaces
perf: Add generic exclude_guest support
perf/x86/intel: Support PERF_PMU_CAP_PASSTHROUGH_VPMU
Manali Shukla (1):
KVM: x86/pmu/svm: Wire up PMU filtering functionality for passthrough
PMU
Mingwei Zhang (24):
perf: core/x86: Forbid PMI handler when guest own PMU
perf: core/x86: Plumb passthrough PMU capability from x86_pmu to
x86_pmu_cap
KVM: x86/pmu: Introduce enable_passthrough_pmu module parameter
KVM: x86/pmu: Plumb through pass-through PMU to vcpu for Intel CPUs
KVM: x86/pmu: Add a helper to check if passthrough PMU is enabled
KVM: x86/pmu: Add host_perf_cap and initialize it in
kvm_x86_vendor_init()
KVM: x86/pmu: Allow RDPMC pass through when all counters exposed to
guest
KVM: x86/pmu: Introduce PMU operator to check if rdpmc passthrough
allowed
KVM: x86/pmu: Create a function prototype to disable MSR interception
KVM: x86/pmu: Avoid legacy vPMU code when accessing global_ctrl in
passthrough vPMU
KVM: x86/pmu: Exclude PMU MSRs in vmx_get_passthrough_msr_slot()
KVM: x86/pmu: Add counter MSR and selector MSR index into struct
kvm_pmc
KVM: x86/pmu: Introduce PMU operation prototypes for save/restore PMU
context
KVM: x86/pmu: Implement the save/restore of PMU state for Intel CPU
KVM: x86/pmu: Make check_pmu_event_filter() an exported function
KVM: x86/pmu: Allow writing to event selector for GP counters if event
is allowed
KVM: x86/pmu: Allow writing to fixed counter selector if counter is
exposed
KVM: x86/pmu: Exclude existing vLBR logic from the passthrough PMU
KVM: x86/pmu: Introduce PMU operator to increment counter
KVM: x86/pmu: Introduce PMU operator for setting counter overflow
KVM: x86/pmu: Implement emulated counter increment for passthrough PMU
KVM: x86/pmu: Update pmc_{read,write}_counter() to disconnect perf API
KVM: x86/pmu: Disconnect counter reprogram logic from passthrough PMU
KVM: nVMX: Add nested virtualization support for passthrough PMU
Sandipan Das (11):
KVM: x86/pmu: Do not mask LVTPC when handling a PMI on AMD platforms
x86/msr: Define PerfCntrGlobalStatusSet register
KVM: x86/pmu: Always set global enable bits in passthrough mode
perf/x86/amd/core: Set passthrough capability for host
KVM: x86/pmu/svm: Set passthrough capability for vcpus
KVM: x86/pmu/svm: Set enable_passthrough_pmu module parameter
KVM: x86/pmu/svm: Allow RDPMC pass through when all counters exposed
to guest
KVM: x86/pmu/svm: Implement callback to disable MSR interception
KVM: x86/pmu/svm: Set GuestOnly bit and clear HostOnly bit when guest
write to event selectors
KVM: x86/pmu/svm: Add registers to direct access list
KVM: x86/pmu/svm: Implement handlers to save and restore context
Sean Christopherson (2):
KVM: x86/pmu: Set enable bits for GP counters in PERF_GLOBAL_CTRL at
"RESET"
KVM: x86: Snapshot if a vCPU's vendor model is AMD vs. Intel
compatible
Xiong Zhang (10):
perf: core/x86: Register a new vector for KVM GUEST PMI
KVM: x86: Extract x86_set_kvm_irq_handler() function
KVM: x86/pmu: Register guest pmi handler for emulated PMU
perf: x86: Add x86 function to switch PMI handler
KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL
KVM: x86/pmu: Switch IA32_PERF_GLOBAL_CTRL at VM boundary
KVM: x86/pmu: Switch PMI handler at KVM context switch boundary
KVM: x86/pmu: Grab x86 core PMU for passthrough PMU VM
KVM: x86/pmu: Call perf_guest_enter() at PMU context switch
KVM: x86/pmu: Add support for PMU context switch at VM-exit/enter
arch/x86/events/amd/core.c | 3 +
arch/x86/events/core.c | 41 ++++-
arch/x86/events/intel/core.c | 6 +
arch/x86/events/perf_event.h | 1 +
arch/x86/include/asm/hardirq.h | 1 +
arch/x86/include/asm/idtentry.h | 1 +
arch/x86/include/asm/irq.h | 2 +-
arch/x86/include/asm/irq_vectors.h | 5 +-
arch/x86/include/asm/kvm-x86-pmu-ops.h | 6 +
arch/x86/include/asm/kvm_host.h | 10 ++
arch/x86/include/asm/msr-index.h | 2 +
arch/x86/include/asm/perf_event.h | 4 +
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kernel/idt.c | 1 +
arch/x86/kernel/irq.c | 36 ++++-
arch/x86/kvm/cpuid.c | 4 +
arch/x86/kvm/cpuid.h | 10 ++
arch/x86/kvm/lapic.c | 3 +-
arch/x86/kvm/mmu/mmu.c | 2 +-
arch/x86/kvm/pmu.c | 168 ++++++++++++++++++-
arch/x86/kvm/pmu.h | 47 ++++++
arch/x86/kvm/svm/pmu.c | 112 ++++++++++++-
arch/x86/kvm/svm/svm.c | 23 +++
arch/x86/kvm/svm/svm.h | 2 +-
arch/x86/kvm/vmx/capabilities.h | 1 +
arch/x86/kvm/vmx/nested.c | 52 ++++++
arch/x86/kvm/vmx/pmu_intel.c | 192 ++++++++++++++++++++--
arch/x86/kvm/vmx/vmx.c | 197 +++++++++++++++++++----
arch/x86/kvm/vmx/vmx.h | 3 +-
arch/x86/kvm/x86.c | 47 +++++-
arch/x86/kvm/x86.h | 1 +
include/linux/perf_event.h | 18 +++
kernel/events/core.c | 176 ++++++++++++++++++++
tools/arch/x86/include/asm/irq_vectors.h | 3 +-
34 files changed, 1120 insertions(+), 61 deletions(-)
base-commit: fec50db7033ea478773b159e0e2efb135270e3b7
--
2.45.0.rc1.225.g2a3ae87e7f-goog
next reply other threads:[~2024-05-06 5:30 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 5:29 Mingwei Zhang [this message]
2024-05-06 5:29 ` [PATCH v2 01/54] KVM: x86/pmu: Set enable bits for GP counters in PERF_GLOBAL_CTRL at "RESET" Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 02/54] KVM: x86: Snapshot if a vCPU's vendor model is AMD vs. Intel compatible Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 03/54] KVM: x86/pmu: Do not mask LVTPC when handling a PMI on AMD platforms Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 04/54] x86/msr: Define PerfCntrGlobalStatusSet register Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 05/54] x86/msr: Introduce MSR_CORE_PERF_GLOBAL_STATUS_SET Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 06/54] perf: Support get/put passthrough PMU interfaces Mingwei Zhang
2024-05-07 8:31 ` Peter Zijlstra
2024-05-08 4:13 ` Zhang, Xiong Y
2024-05-07 8:41 ` Peter Zijlstra
2024-05-08 4:54 ` Zhang, Xiong Y
2024-05-08 8:32 ` Peter Zijlstra
2024-05-06 5:29 ` [PATCH v2 07/54] perf: Add generic exclude_guest support Mingwei Zhang
2024-05-07 8:58 ` Peter Zijlstra
2024-05-06 5:29 ` [PATCH v2 08/54] perf/x86/intel: Support PERF_PMU_CAP_PASSTHROUGH_VPMU Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 09/54] perf: core/x86: Register a new vector for KVM GUEST PMI Mingwei Zhang
2024-05-07 9:12 ` Peter Zijlstra
2024-05-08 10:06 ` Yanfei Xu
2024-05-06 5:29 ` [PATCH v2 10/54] KVM: x86: Extract x86_set_kvm_irq_handler() function Mingwei Zhang
2024-05-07 9:18 ` Peter Zijlstra
2024-05-08 8:57 ` Zhang, Xiong Y
2024-05-06 5:29 ` [PATCH v2 11/54] KVM: x86/pmu: Register guest pmi handler for emulated PMU Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 12/54] perf: x86: Add x86 function to switch PMI handler Mingwei Zhang
2024-05-07 9:22 ` Peter Zijlstra
2024-05-08 6:58 ` Zhang, Xiong Y
2024-05-08 8:37 ` Peter Zijlstra
2024-05-09 7:30 ` Zhang, Xiong Y
2024-05-07 21:40 ` Chen, Zide
2024-05-08 3:44 ` Mi, Dapeng
2024-05-06 5:29 ` [PATCH v2 13/54] perf: core/x86: Forbid PMI handler when guest own PMU Mingwei Zhang
2024-05-07 9:33 ` Peter Zijlstra
2024-05-09 7:39 ` Zhang, Xiong Y
2024-05-06 5:29 ` [PATCH v2 14/54] perf: core/x86: Plumb passthrough PMU capability from x86_pmu to x86_pmu_cap Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 15/54] KVM: x86/pmu: Introduce enable_passthrough_pmu module parameter Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 16/54] KVM: x86/pmu: Plumb through pass-through PMU to vcpu for Intel CPUs Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 17/54] KVM: x86/pmu: Always set global enable bits in passthrough mode Mingwei Zhang
2024-05-08 4:18 ` Mi, Dapeng
2024-05-08 4:36 ` Mingwei Zhang
2024-05-08 6:27 ` Mi, Dapeng
2024-05-08 14:13 ` Sean Christopherson
2024-05-09 0:13 ` Mingwei Zhang
2024-05-09 0:30 ` Mi, Dapeng
2024-05-09 0:38 ` Mi, Dapeng
2024-05-06 5:29 ` [PATCH v2 18/54] KVM: x86/pmu: Add a helper to check if passthrough PMU is enabled Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 19/54] KVM: x86/pmu: Add host_perf_cap and initialize it in kvm_x86_vendor_init() Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 20/54] KVM: x86/pmu: Allow RDPMC pass through when all counters exposed to guest Mingwei Zhang
2024-05-08 21:55 ` Chen, Zide
2024-05-06 5:29 ` [PATCH v2 21/54] KVM: x86/pmu: Introduce macro PMU_CAP_PERF_METRICS Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 22/54] KVM: x86/pmu: Introduce PMU operator to check if rdpmc passthrough allowed Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 23/54] KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 24/54] KVM: x86/pmu: Create a function prototype to disable MSR interception Mingwei Zhang
2024-05-08 22:03 ` Chen, Zide
2024-05-06 5:29 ` [PATCH v2 25/54] KVM: x86/pmu: Add intel_passthrough_pmu_msrs() to pass-through PMU MSRs Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 26/54] KVM: x86/pmu: Avoid legacy vPMU code when accessing global_ctrl in passthrough vPMU Mingwei Zhang
2024-05-08 21:48 ` Chen, Zide
2024-05-09 0:43 ` Mi, Dapeng
2024-05-09 1:29 ` Chen, Zide
2024-05-09 2:58 ` Mi, Dapeng
2024-05-06 5:29 ` [PATCH v2 27/54] KVM: x86/pmu: Exclude PMU MSRs in vmx_get_passthrough_msr_slot() Mingwei Zhang
2024-05-14 7:33 ` Mi, Dapeng
2024-05-06 5:29 ` [PATCH v2 28/54] KVM: x86/pmu: Add counter MSR and selector MSR index into struct kvm_pmc Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 29/54] KVM: x86/pmu: Introduce PMU operation prototypes for save/restore PMU context Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 30/54] KVM: x86/pmu: Implement the save/restore of PMU state for Intel CPU Mingwei Zhang
2024-05-14 8:08 ` Mi, Dapeng
2024-05-06 5:29 ` [PATCH v2 31/54] KVM: x86/pmu: Make check_pmu_event_filter() an exported function Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 32/54] KVM: x86/pmu: Allow writing to event selector for GP counters if event is allowed Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 33/54] KVM: x86/pmu: Allow writing to fixed counter selector if counter is exposed Mingwei Zhang
2024-05-06 5:29 ` [PATCH v2 34/54] KVM: x86/pmu: Switch IA32_PERF_GLOBAL_CTRL at VM boundary Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 35/54] KVM: x86/pmu: Exclude existing vLBR logic from the passthrough PMU Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 36/54] KVM: x86/pmu: Switch PMI handler at KVM context switch boundary Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 37/54] KVM: x86/pmu: Grab x86 core PMU for passthrough PMU VM Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 38/54] KVM: x86/pmu: Call perf_guest_enter() at PMU context switch Mingwei Zhang
2024-05-07 9:39 ` Peter Zijlstra
2024-05-08 4:22 ` Mi, Dapeng
2024-05-06 5:30 ` [PATCH v2 39/54] KVM: x86/pmu: Add support for PMU context switch at VM-exit/enter Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 40/54] KVM: x86/pmu: Introduce PMU operator to increment counter Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 41/54] KVM: x86/pmu: Introduce PMU operator for setting counter overflow Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 42/54] KVM: x86/pmu: Implement emulated counter increment for passthrough PMU Mingwei Zhang
2024-05-08 18:28 ` Chen, Zide
2024-05-09 1:11 ` Mi, Dapeng
2024-05-06 5:30 ` [PATCH v2 43/54] KVM: x86/pmu: Update pmc_{read,write}_counter() to disconnect perf API Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 44/54] KVM: x86/pmu: Disconnect counter reprogram logic from passthrough PMU Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 45/54] KVM: nVMX: Add nested virtualization support for " Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 46/54] perf/x86/amd/core: Set passthrough capability for host Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 47/54] KVM: x86/pmu/svm: Set passthrough capability for vcpus Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 48/54] KVM: x86/pmu/svm: Set enable_passthrough_pmu module parameter Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 49/54] KVM: x86/pmu/svm: Allow RDPMC pass through when all counters exposed to guest Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 50/54] KVM: x86/pmu/svm: Implement callback to disable MSR interception Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 51/54] KVM: x86/pmu/svm: Set GuestOnly bit and clear HostOnly bit when guest write to event selectors Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 52/54] KVM: x86/pmu/svm: Add registers to direct access list Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 53/54] KVM: x86/pmu/svm: Implement handlers to save and restore context Mingwei Zhang
2024-05-06 5:30 ` [PATCH v2 54/54] KVM: x86/pmu/svm: Wire up PMU filtering functionality for passthrough PMU Mingwei Zhang
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