From: Zhao Liu <zhao1.liu@intel.com>
To: "Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>,
Babu Moger <babu.moger@amd.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Dapeng Mi <dapeng1.mi@intel.com>,
Yongwei Ma <yongwei.ma@intel.com>, Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v11 12/21] i386: Introduce module level cpu topology to CPUX86State
Date: Wed, 24 Apr 2024 23:49:20 +0800 [thread overview]
Message-ID: <20240424154929.1487382-13-zhao1.liu@intel.com> (raw)
In-Reply-To: <20240424154929.1487382-1-zhao1.liu@intel.com>
Intel CPUs implement module level on hybrid client products (e.g.,
ADL-N, MTL, etc) and E-core server products.
A module contains a set of cores that share certain resources (in
current products, the resource usually includes L2 cache, as well as
module scoped features and MSRs).
Module level support is the prerequisite for L2 cache topology on
module level. With module level, we can implement the Guest's CPU
topology and future cache topology to be consistent with the Host's on
Intel hybrid client/E-core server platforms.
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Co-developed-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
---
Changes since v7:
* Mapped x86 module to smp module instead of cluster.
* Re-wrote the commit message to explain the reason why we needs module
level.
* Dropped Michael/Babu's ACKed/Tested tags since the code change.
* Re-added Yongwei's Tested tag For his re-testing.
Changes since v1:
* The background of the introduction of the "cluster" parameter and its
exact meaning were revised according to Yanan's explanation. (Yanan)
---
hw/i386/x86.c | 5 +++++
target/i386/cpu.c | 1 +
target/i386/cpu.h | 3 +++
3 files changed, 9 insertions(+)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 004627fa8985..3b5cf75d5bf3 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -313,6 +313,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
init_topo_info(&topo_info, x86ms);
+ if (ms->smp.modules > 1) {
+ env->nr_modules = ms->smp.modules;
+ /* TODO: Expose module level in CPUID[0x1F]. */
+ }
+
if (ms->smp.dies > 1) {
env->nr_dies = ms->smp.dies;
set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 504ec569e0b2..8f34a5b8d726 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7871,6 +7871,7 @@ static void x86_cpu_init_default_topo(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
+ env->nr_modules = 1;
env->nr_dies = 1;
/* SMT, core and package levels are set by default. */
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index fa9b6679387e..630129838c08 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1899,6 +1899,9 @@ typedef struct CPUArchState {
/* Number of dies within this CPU package. */
unsigned nr_dies;
+ /* Number of modules within one die. */
+ unsigned nr_modules;
+
/* Bitmap of available CPU topology levels for this CPU. */
DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX);
} CPUX86State;
--
2.34.1
next prev parent reply other threads:[~2024-04-24 15:37 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-24 15:49 [PATCH v11 00/21] i386: Introduce smp.modules and clean up cache topology Zhao Liu
2024-04-24 15:49 ` [PATCH v11 01/21] hw/core/machine: Introduce the module as a CPU topology level Zhao Liu
2024-04-24 15:49 ` [PATCH v11 02/21] hw/core/machine: Support modules in -smp Zhao Liu
2024-04-24 15:49 ` [PATCH v11 03/21] hw/core: Introduce module-id as the topology subindex Zhao Liu
2024-04-24 15:49 ` [PATCH v11 04/21] hw/core: Support module-id in numa configuration Zhao Liu
2024-04-24 15:49 ` [PATCH v11 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2024-04-24 15:49 ` [PATCH v11 06/21] i386/cpu: Use APIC ID info to encode cache topo in CPUID[4] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 07/21] i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2024-04-24 15:49 ` [PATCH v11 09/21] i386/cpu: Introduce bitmap to cache available CPU topology levels Zhao Liu
2024-04-24 15:49 ` [PATCH v11 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 11/21] i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2024-04-24 15:49 ` Zhao Liu [this message]
2024-04-24 15:49 ` [PATCH v11 13/21] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2024-04-24 15:49 ` [PATCH v11 14/21] i386: Expose module level in CPUID[0x1F] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 15/21] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2024-04-24 15:49 ` [PATCH v11 16/21] i386/cpu: Introduce module-id to X86CPU Zhao Liu
2024-04-24 15:49 ` [PATCH v11 17/21] tests: Add test case of APIC ID for module level parsing Zhao Liu
2024-04-24 15:49 ` [PATCH v11 18/21] hw/i386/pc: Support smp.modules for x86 PC machine Zhao Liu
2024-04-24 15:49 ` [PATCH v11 19/21] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2024-04-24 15:49 ` [PATCH v11 20/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2024-04-24 15:49 ` [PATCH v11 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2024-04-25 8:06 ` [PATCH v11 00/21] i386: Introduce smp.modules and clean up cache topology Philippe Mathieu-Daudé
2024-04-25 13:30 ` Zhao Liu
2024-05-15 14:48 ` Zhao Liu
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