From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Ajay Kaher <ajay.kaher@broadcom.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Anup Patel <anup@brainfault.org>,
samuel.holland@sifive.com,
Conor Dooley <conor.dooley@microchip.com>,
Juergen Gross <jgross@suse.com>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Shuah Khan <shuah@kernel.org>,
virtualization@lists.linux.dev, Will Deacon <will@kernel.org>,
x86@kernel.org
Subject: [PATCH v8 04/24] drivers/perf: riscv: Use BIT macro for shifting operations
Date: Sat, 20 Apr 2024 08:17:20 -0700 [thread overview]
Message-ID: <20240420151741.962500-5-atishp@rivosinc.com> (raw)
In-Reply-To: <20240420151741.962500-1-atishp@rivosinc.com>
It is a good practice to use BIT() instead of (1 << x).
Replace the current usages with BIT().
Take this opportunity to replace few (1UL << x) with BIT() as well
for consistency.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/sbi.h | 20 ++++++++++----------
drivers/perf/riscv_pmu_sbi.c | 2 +-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index ef8311dafb91..4afa2cd01bae 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type {
#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
/* Flags defined for config matching function */
-#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0)
-#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1)
-#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2)
-#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3)
-#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4)
-#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5)
-#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6)
-#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7)
+#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0)
+#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1)
+#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2)
+#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3)
+#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4)
+#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5)
+#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6)
+#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7)
/* Flags defined for counter start function */
-#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
+#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
/* Flags defined for counter stop function */
-#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
+#define SBI_PMU_STOP_FLAG_RESET BIT(0)
enum sbi_ext_dbcn_fid {
SBI_EXT_DBCN_CONSOLE_WRITE = 0,
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 1823ffb25d35..f23501898657 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
cmask = 1;
} else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) {
cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH;
- cmask = 1UL << (CSR_INSTRET - CSR_CYCLE);
+ cmask = BIT(CSR_INSTRET - CSR_CYCLE);
}
}
--
2.34.1
next prev parent reply other threads:[~2024-04-19 23:47 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-20 15:17 [PATCH v8 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Atish Patra
2024-04-20 15:17 ` [PATCH v8 01/24] RISC-V: Fix the typo in Scountovf CSR name Atish Patra
2024-04-20 15:17 ` [PATCH v8 02/24] RISC-V: Add FIRMWARE_READ_HI definition Atish Patra
2024-04-20 15:17 ` [PATCH v8 03/24] drivers/perf: riscv: Read upper bits of a firmware counter Atish Patra
2024-04-20 15:17 ` Atish Patra [this message]
2024-04-20 15:17 ` [PATCH v8 05/24] RISC-V: Add SBI PMU snapshot definitions Atish Patra
2024-04-20 15:17 ` [PATCH v8 06/24] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Atish Patra
2024-04-20 15:17 ` [PATCH v8 07/24] RISC-V: Use the minor version mask while computing sbi version Atish Patra
2024-04-20 15:17 ` [PATCH v8 08/24] drivers/perf: riscv: Fix counter mask iteration for RV32 Atish Patra
2024-04-20 0:37 ` Samuel Holland
2024-04-20 1:08 ` Atish Kumar Patra
2024-04-20 15:17 ` [PATCH v8 09/24] drivers/perf: riscv: Implement SBI PMU snapshot function Atish Patra
2024-04-22 16:06 ` Samuel Holland
2024-04-23 20:34 ` Atish Kumar Patra
2024-04-20 15:17 ` [PATCH v8 10/24] RISC-V: KVM: Fix the initial sample period value Atish Patra
2024-04-22 5:24 ` Anup Patel
2024-04-20 15:17 ` [PATCH v8 11/24] RISC-V: KVM: No need to update the counter value during reset Atish Patra
2024-04-20 15:17 ` [PATCH v8 12/24] RISC-V: KVM: No need to exit to the user space if perf event failed Atish Patra
2024-04-20 15:17 ` [PATCH v8 13/24] RISC-V: KVM: Implement SBI PMU Snapshot feature Atish Patra
2024-04-20 15:17 ` [PATCH v8 14/24] RISC-V: KVM: Add perf sampling support for guests Atish Patra
2024-04-20 15:17 ` [PATCH v8 15/24] RISC-V: KVM: Support 64 bit firmware counters on RV32 Atish Patra
2024-04-20 15:17 ` [PATCH v8 16/24] RISC-V: KVM: Improve firmware counter read function Atish Patra
2024-04-22 5:26 ` Anup Patel
2024-04-20 15:17 ` [PATCH v8 17/24] KVM: riscv: selftests: Move sbi definitions to its own header file Atish Patra
2024-04-22 5:27 ` Anup Patel
2024-04-23 8:57 ` Muhammad Usama Anjum
2024-04-20 15:17 ` [PATCH v8 18/24] KVM: riscv: selftests: Add helper functions for extension checks Atish Patra
2024-04-22 5:29 ` Anup Patel
2024-04-23 8:57 ` Muhammad Usama Anjum
2024-04-20 15:17 ` [PATCH v8 19/24] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Atish Patra
2024-04-23 8:58 ` Muhammad Usama Anjum
2024-04-20 15:17 ` [PATCH v8 20/24] KVM: riscv: selftests: Add SBI PMU extension definitions Atish Patra
2024-04-23 8:58 ` Muhammad Usama Anjum
2024-04-20 15:17 ` [PATCH v8 21/24] KVM: riscv: selftests: Add SBI PMU selftest Atish Patra
2024-04-23 8:59 ` Muhammad Usama Anjum
2024-04-20 15:17 ` [PATCH v8 22/24] KVM: riscv: selftests: Add a test for PMU snapshot functionality Atish Patra
2024-04-23 9:00 ` Muhammad Usama Anjum
2024-04-20 15:17 ` [PATCH v8 23/24] KVM: riscv: selftests: Add a test for counter overflow Atish Patra
2024-04-23 9:00 ` Muhammad Usama Anjum
2024-04-20 15:17 ` [PATCH v8 24/24] KVM: riscv: selftests: Add commandline option for SBI PMU test Atish Patra
2024-04-22 5:32 ` Anup Patel
2024-04-23 9:03 ` Muhammad Usama Anjum
2024-04-23 10:56 ` Andrew Jones
2024-04-22 9:59 ` [PATCH v8 00/24] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest Anup Patel
2024-04-30 5:54 ` Anup Patel
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