From: "Chan Kim" <ckim@etri.re.kr>
To: <kernelnewbies@kernelnewbies.org>
Subject: In device tree, can't understand 'ranges' property of PCIe root complex node
Date: Mon, 6 Feb 2023 21:06:59 +0900 [thread overview]
Message-ID: <03ab01d93a23$83ef3a60$8bcdaf20$@etri.re.kr> (raw)
Hello all,
For example in linux-5.15.68's arch/arm64/boot/dts/ti/k3-am64-main.dtsi,
&cbass_main {
... skip ...
pcie0_rc: pcie@f102000 {
compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
reg = <0x00 0x0f102000 0x00 0x1000>,
<0x00 0x0f100000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x68000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
... skip ...
#address-cells = <3>;
#size-cells = <2>;
...skip ...
msi-map = <0x0 &gic_its 0x0 0x10000>;
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00
0x0010000>,
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00
0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
};
};
the 'ranges' property says
- IO space starting at address 0x68001000 with size 64KiB is mapped to the
parent bus address 0x68001000.
- a 32 bit memory address space starting with address 0x68011000 and size
0x7fef000 is mapped to parent bus address 0x68011000.
The device tree document says these addresses are all physical.
What I can't understand is :
I know the BIOS will set the BAR addresses during the enumeration process.
This is allocating the endpoint's function to a certain PCIe bus address and
I guess setting BAR can be done without this 'ranges' information(it will
assign free address range for that device according to the device's need).
By the time linux kernel later reads this 'ranges' property, the BIOS (or
bootloader) has already assigned different PCIe address to that device.
Then, how is this 'ranges' property used by the kernel?
Thank you.
Chan Kim
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next reply other threads:[~2023-02-06 14:50 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 12:06 Chan Kim [this message]
2023-02-14 5:30 ` In device tree, can't understand 'ranges' property of PCIe root complex node Chan Kim
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