From: "Dong, Zhanjun" <zhanjun.dong@intel.com>
To: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v8 2/6] drm/xe/guc: Add XE_LP steered register lists
Date: Tue, 14 May 2024 19:00:10 -0400 [thread overview]
Message-ID: <54f87429-f44e-4a68-8f2e-3988f7927e4a@intel.com> (raw)
In-Reply-To: <4d68b6cc674d6350fc0e0ef1995c5ae00beaa691.camel@intel.com>
On 2024-05-10 8:17 p.m., Teres Alexis, Alan Previn wrote:
> only a couple of nits, so,
> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
>
> On Mon, 2024-05-06 at 18:47 -0700, Zhanjun Dong wrote:
>> Add the ability for runtime allocation and freeing of
>> steered register list extentions that depend on the
>> detected HW config fuses.
>>
> alan:snip
>> +static void
>> +guc_capture_alloc_steered_lists(struct xe_guc *guc, const struct __guc_mmio_reg_descr_group *lists)
>> +{
>> + struct xe_gt *gt = guc_to_gt(guc);
>> + u16 slice, subslice;
>> + int iter, i, num_steer_regs, num_tot_regs = 0;
>> + const struct __guc_mmio_reg_descr_group *list;
>> + struct __guc_mmio_reg_descr_group *extlists;
>> + struct __guc_mmio_reg_descr *extarray;
>> + bool has_xehpg_extregs;
>> + struct drm_device *drm = >_to_xe(gt)->drm;
> alan: nit: order vars as reverse christmas tree. I'm not sure if this is a hard rule,
> I've seen many review comments about this but cant find a hard rule in kernel doc.
> I wasnt paying attention to this earlier and realize that Patch #1 has at least 4 functions
> with this issue. I'm going to leave at your discretion since i assume this is a nit.
>
in Xe folder, egrep ">_to_xe\(.*\)->drm" *.c
we have many
>> +
>> + /* steered registers currently only exist for the render-class */
>> + list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
>> + GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
>> + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE);
>> + /* skip if extlists was previously allocated */
>> + if (!list || guc->capture->extlists)
>> + return;
>> +
>> + has_xehpg_extregs = GRAPHICS_VERx100(gt_to_xe(gt)) >= 1255;
>> +
>> + num_steer_regs = ARRAY_SIZE(xe_extregs);
>> + if (has_xehpg_extregs)
>> + num_steer_regs += ARRAY_SIZE(xehpg_extregs);
>> +
>> + num_tot_regs += num_steer_regs * bitmap_weight(gt->fuse_topo.g_dss_mask,
>> + sizeof(gt->fuse_topo.g_dss_mask) * 8);
> alan: nit: a bit confusing we are using "num_tot_regs +=" when its the first use of this
> variable after init to zero, so just "num_tot_regs =" is fine here.
Typo, will changed to =
>
> alan:snip
>
next prev parent reply other threads:[~2024-05-14 23:00 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 1:47 [PATCH v8 0/6] drm/xe/guc: Add GuC based register capture for error capture Zhanjun Dong
2024-05-07 1:47 ` [PATCH v8 1/6] drm/xe/guc: Prepare GuC register list and update ADS size " Zhanjun Dong
2024-05-10 18:43 ` Teres Alexis, Alan Previn
2024-05-14 22:44 ` Dong, Zhanjun
2024-05-10 18:58 ` Teres Alexis, Alan Previn
2024-05-07 1:47 ` [PATCH v8 2/6] drm/xe/guc: Add XE_LP steered register lists Zhanjun Dong
2024-05-11 0:17 ` Teres Alexis, Alan Previn
2024-05-14 23:00 ` Dong, Zhanjun [this message]
2024-05-07 1:47 ` [PATCH v8 3/6] drm/xe/guc: Add capture size check in GuC log buffer Zhanjun Dong
2024-05-08 22:57 ` Teres Alexis, Alan Previn
2024-05-15 21:39 ` Dong, Zhanjun
2024-05-07 1:47 ` [PATCH v8 4/6] drm/xe/guc: Extract GuC error capture lists Zhanjun Dong
2024-05-11 1:43 ` Teres Alexis, Alan Previn
2024-05-15 21:45 ` Dong, Zhanjun
2024-05-15 21:55 ` Dong, Zhanjun
2024-05-07 1:47 ` [PATCH v8 5/6] drm/xe/guc: Pre-allocate output nodes for extraction Zhanjun Dong
2024-05-11 18:07 ` Teres Alexis, Alan Previn
2024-05-07 1:47 ` [PATCH v8 6/6] drm/xe/guc: Plumb GuC-capture into dev coredump Zhanjun Dong
2024-05-11 20:25 ` Teres Alexis, Alan Previn
2024-05-07 4:17 ` ✓ CI.Patch_applied: success for drm/xe/guc: Add GuC based register capture for error capture (rev8) Patchwork
2024-05-07 4:18 ` ✗ CI.checkpatch: warning " Patchwork
2024-05-07 4:19 ` ✓ CI.KUnit: success " Patchwork
2024-05-07 4:31 ` ✓ CI.Build: " Patchwork
2024-05-07 4:41 ` ✗ CI.Hooks: failure " Patchwork
2024-05-07 4:49 ` ✓ CI.checksparse: success " Patchwork
2024-05-07 5:24 ` ✗ CI.BAT: failure " Patchwork
2024-05-07 9:35 ` ✗ CI.FULL: " Patchwork
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