From: Riana Tauro <riana.tauro@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: <intel-xe@lists.freedesktop.org>, <anshuman.gupta@intel.com>,
<vinay.belgaumkar@intel.com>
Subject: Re: [PATCH 1/2] drm/xe: change the power gating register names
Date: Wed, 15 May 2024 10:32:20 +0530 [thread overview]
Message-ID: <405b41a3-0b76-458f-84f0-295a3cb7f78f@intel.com> (raw)
In-Reply-To: <ZkQlAj0h4v1s1u9I@intel.com>
Hi Rodrigo
On 5/15/2024 8:29 AM, Rodrigo Vivi wrote:
> On Tue, May 14, 2024 at 12:13:08PM +0530, Riana Tauro wrote:
>> change
>
> Probably good to start with Capital letter here and in the subject.
>
> (not that I follow good standards myself on this, right Francois? ;) )
>
> power gating vd registers naming to n-form
>
> reading here I was thinking: What's VD? What's n-form?
> Only after reading the patch it made some sense.
>
> Perhaps only a message saying:
> "Standardize power gate registers." should be enough.Thanks for the review. Will re-word the commit message
Thanks
Riana
>
>> change PG_ENABLE to POWERGATE_ENABLE.
>>
>> No functional changes
>>
>> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 8 +++-----
>> drivers/gpu/drm/xe/xe_gt_idle.c | 2 +-
>> drivers/gpu/drm/xe/xe_wa.c | 10 +++++-----
>> 3 files changed, 9 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 9cacdcfe27ff..7c173db7d585 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -316,11 +316,9 @@
>>
>> #define FORCEWAKE_GT XE_REG(0xa188)
>>
>> -#define PG_ENABLE XE_REG(0xa210)
>> -#define VD2_MFXVDENC_POWERGATE_ENABLE REG_BIT(8)
>> -#define VD2_HCP_POWERGATE_ENABLE REG_BIT(7)
>> -#define VD0_MFXVDENC_POWERGATE_ENABLE REG_BIT(4)
>> -#define VD0_HCP_POWERGATE_ENABLE REG_BIT(3)
>> +#define POWERGATE_ENABLE XE_REG(0xa210)
>> +#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n))
>> +#define VDN_MFXVDENC_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n))
>>
>> #define CTC_MODE XE_REG(0xa26c)
>> #define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1)
>> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
>> index a4f6f0a96d05..4384f7e80258 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_idle.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_idle.c
>> @@ -202,7 +202,7 @@ void xe_gt_idle_disable_c6(struct xe_gt *gt)
>> xe_device_assert_mem_access(gt_to_xe(gt));
>> xe_force_wake_assert_held(gt_to_fw(gt), XE_FORCEWAKE_ALL);
>>
>> - xe_mmio_write32(gt, PG_ENABLE, 0);
>> + xe_mmio_write32(gt, POWERGATE_ENABLE, 0);
>> xe_mmio_write32(gt, RC_CONTROL, 0);
>> xe_mmio_write32(gt, RC_STATE, 0);
>> }
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index 05db53c1448c..64bc595fc727 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -238,11 +238,11 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>> },
>> { XE_RTP_NAME("14020316580"),
>> XE_RTP_RULES(MEDIA_VERSION(1301)),
>> - XE_RTP_ACTIONS(CLR(PG_ENABLE,
>> - VD0_HCP_POWERGATE_ENABLE |
>> - VD0_MFXVDENC_POWERGATE_ENABLE |
>> - VD2_HCP_POWERGATE_ENABLE |
>> - VD2_MFXVDENC_POWERGATE_ENABLE)),
>> + XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,
>> + VDN_HCP_POWERGATE_ENABLE(0) |
>> + VDN_MFXVDENC_POWERGATE_ENABLE(0) |
>> + VDN_HCP_POWERGATE_ENABLE(2) |
>> + VDN_MFXVDENC_POWERGATE_ENABLE(2))),
>
> For the patch itself everything looks good.
> With the commit message improved:
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>> },
>> { XE_RTP_NAME("14019449301"),
>> XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
>> --
>> 2.40.0
>>
next prev parent reply other threads:[~2024-05-15 5:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-14 6:43 [PATCH 0/2] Enable Coarse Power Gating Riana Tauro
2024-05-14 6:36 ` ✓ CI.Patch_applied: success for " Patchwork
2024-05-14 6:36 ` ✓ CI.checkpatch: " Patchwork
2024-05-14 6:37 ` ✓ CI.KUnit: " Patchwork
2024-05-14 6:43 ` [PATCH 1/2] drm/xe: change the power gating register names Riana Tauro
2024-05-15 2:59 ` Rodrigo Vivi
2024-05-15 5:02 ` Riana Tauro [this message]
2024-05-14 6:43 ` [PATCH 2/2] RFC drm/xe: Enable Coarse Power Gating Riana Tauro
2024-05-15 3:11 ` Rodrigo Vivi
2024-05-15 7:35 ` Riana Tauro
2024-05-14 6:49 ` ✓ CI.Build: success for " Patchwork
2024-05-14 6:51 ` ✓ CI.Hooks: " Patchwork
2024-05-14 6:53 ` ✓ CI.checksparse: " Patchwork
2024-05-14 7:15 ` ✓ CI.BAT: " Patchwork
2024-05-14 8:25 ` ✗ CI.FULL: failure " Patchwork
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