From: Matt Roper <matthew.d.roper@intel.com>
To: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v2 1/4] drm/xe: Minor cleanup in LRC handling
Date: Tue, 7 May 2024 15:21:05 -0700 [thread overview]
Message-ID: <20240507222105.GH5615@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20240506171111.16280-2-niranjana.vishwanathapura@intel.com>
On Mon, May 06, 2024 at 10:11:02AM -0700, Niranjana Vishwanathapura wrote:
> Properly define register fields and remove redundant
> lower_32_bits().
>
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 4 ++--
> drivers/gpu/drm/xe/xe_lrc.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 97d2aed63e01..7e1b0fd68275 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -44,9 +44,10 @@
> #define GSCCS_RING_BASE 0x11a000
>
> #define RING_TAIL(base) XE_REG((base) + 0x30)
> +#define TAIL_ADDR REG_GENMASK(20, 3)
>
> #define RING_HEAD(base) XE_REG((base) + 0x34)
> -#define HEAD_ADDR 0x001FFFFC
> +#define HEAD_ADDR REG_GENMASK(20, 2)
>
> #define RING_START(base) XE_REG((base) + 0x38)
>
> @@ -136,7 +137,6 @@
> #define RING_VALID_MASK 0x00000001
> #define RING_VALID 0x00000001
> #define STOP_RING REG_BIT(8)
> -#define TAIL_ADDR 0x001FFFF8
>
> #define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8)
> #define CSBE_DEBUG_STATUS(base) XE_REG((base) + 0x3fc)
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 2066d34ddf0b..f759f4c10914 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -1354,7 +1354,7 @@ struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc)
> if (!snapshot)
> return NULL;
>
> - snapshot->context_desc = lower_32_bits(xe_lrc_ggtt_addr(lrc));
> + snapshot->context_desc = xe_lrc_ggtt_addr(lrc);
> snapshot->head = xe_lrc_ring_head(lrc);
> snapshot->tail.internal = lrc->ring.tail;
> snapshot->tail.memory = xe_lrc_read_ctx_reg(lrc, CTX_RING_TAIL);
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
next prev parent reply other threads:[~2024-05-07 22:21 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 17:11 [PATCH v2 0/4] drm/xe: Add Indirect Ring State support Niranjana Vishwanathapura
2024-05-06 17:11 ` [PATCH v2 1/4] drm/xe: Minor cleanup in LRC handling Niranjana Vishwanathapura
2024-05-07 22:21 ` Matt Roper [this message]
2024-05-06 17:11 ` [PATCH v2 2/4] drm/xe: Add Indirect Ring State support Niranjana Vishwanathapura
2024-05-07 22:10 ` Matt Roper
2024-05-06 17:11 ` [PATCH v2 3/4] drm/xe: Dump Indirect Ring State registers Niranjana Vishwanathapura
2024-05-07 22:17 ` Matt Roper
2024-05-06 17:11 ` [PATCH v2 4/4] drm/xe/xe2: Enable Indirect Ring State support for Xe2 Niranjana Vishwanathapura
2024-05-07 22:20 ` Matt Roper
2024-05-06 19:13 ` ✓ CI.Patch_applied: success for drm/xe: Add Indirect Ring State support (rev2) Patchwork
2024-05-06 19:13 ` ✓ CI.checkpatch: " Patchwork
2024-05-06 19:14 ` ✓ CI.KUnit: " Patchwork
2024-05-06 19:26 ` ✓ CI.Build: " Patchwork
2024-05-06 19:31 ` ✓ CI.Hooks: " Patchwork
2024-05-06 19:45 ` ✓ CI.checksparse: " Patchwork
2024-05-06 20:35 ` ✓ CI.BAT: " Patchwork
2024-05-06 23:29 ` ✗ CI.FULL: failure " Patchwork
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